SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL
First Claim
1. A semiconductor device comprising a memory cell, the memory cell including a first transistor and a second transistor,wherein the first transistor comprises a first semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode,wherein the second transistor comprises a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode,wherein the second semiconductor layer includes an oxide semiconductor material,wherein one of the second source electrode and the second drain electrode is electrically connected to the first gate electrode, andwherein charge accumulated in the first gate electrode is discharged by irradiating the second semiconductor layer with an ultraviolet light.
1 Assignment
0 Petitions
Accused Products
Abstract
A nonvolatile memory includes a memory cell including a first transistor and a second transistor. The first transistor includes a first channel, a first gate electrode, a first source electrode, and a first drain electrode. The second transistor includes a second channel made of oxide semiconductor material, a second gate electrode, a second source electrode, and a second drain electrode. One of the second source electrode and the second drain electrode is electrically connected to the first gate electrode. Data writing in the memory cell is done by raising the potential of a node between one of the second source electrode and the second drain electrode and the first gate electrode. Data erasure in the memory cell is done by irradiating the second channel with ultraviolet light and lowering the potential of the node.
215 Citations
32 Claims
-
1. A semiconductor device comprising a memory cell, the memory cell including a first transistor and a second transistor,
wherein the first transistor comprises a first semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode, wherein the second transistor comprises a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode, wherein the second semiconductor layer includes an oxide semiconductor material, wherein one of the second source electrode and the second drain electrode is electrically connected to the first gate electrode, and wherein charge accumulated in the first gate electrode is discharged by irradiating the second semiconductor layer with an ultraviolet light.
-
6. A semiconductor device comprising a memory cell, the memory cell including a first transistor, a second transistor, and a third transistor,
wherein the first transistor comprises a first semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode, wherein the second transistor comprises a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode, wherein the third transistor comprises a third semiconductor layer, a third gate electrode, a third source electrode, and a third drain electrode, wherein the second semiconductor layer includes an oxide semiconductor material, wherein one of the second source electrode and the second drain electrode is electrically connected to the first gate electrode, wherein one of the first source electrode and the first drain electrode electrically connected to one of the third source electrode and the third drain electrode, and wherein charge accumulated in the first gate electrode is discharged by irradiating the second semiconductor layer with an ultraviolet light.
-
12. A semiconductor device comprising a first memory cell and a second memory cell,
wherein the first memory cell comprises a first transistor, a second transistor, and a first capacitor, wherein the first transistor comprises a first semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode, wherein the second transistor comprises a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode, wherein the second semiconductor layer includes a first oxide semiconductor material, wherein one of the second source electrode and the second drain electrode is electrically connected to the first gate electrode and a first electrode of the first capacitor, wherein the second memory cell comprises a third transistor, a fourth transistor, and a second capacitor, wherein the third transistor comprises a third semiconductor layer, a third gate electrode, a third source electrode, and a third drain electrode, wherein the fourth transistor comprises a fourth semiconductor layer, a fourth gate electrode, a fourth source electrode, and a fourth drain electrode, wherein the fourth semiconductor layer includes a second oxide semiconductor material, wherein one of the fourth source electrode and the fourth drain electrode is electrically connected to the third gate electrode and a first electrode of the second capacitor, wherein one of the first source electrode and the first drain electrode is electrically connected to one of the third source electrode and the third drain electrode, wherein charge accumulated in the first gate electrode is discharged by irradiating the second semiconductor layer with a first ultraviolet light, and wherein charge accumulated in the third gate electrode is discharged by irradiating the fourth semiconductor layer with a second ultraviolet light.
-
20. A semiconductor device comprising a memory cell, the memory cell including a transistor and a capacitor,
wherein the transistor comprises a semiconductor layer, a gate electrode, a source electrode, and a drain electrode, wherein the semiconductor layer includes an oxide semiconductor material, wherein one of the source electrode and the drain electrode is electrically connected to a first electrode of the capacitor, and wherein charge accumulated in the first electrode of the capacitor is discharged by irradiating the semiconductor layer with an ultraviolet light.
-
24. A semiconductor device comprising a memory cell, the memory cell including a first transistor and a second transistor,
wherein the first transistor comprises a first semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode, wherein the second transistor comprises a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode, wherein the second semiconductor layer includes an oxide semiconductor material, wherein one of the second source electrode and the second drain electrode is electrically connected to the first gate electrode, wherein data writing in the memory cell is done by raising a potential of the first gate electrode, or by storing charge in the first gate electrode, and wherein data erasure in the memory cell is done by irradiating the second semiconductor layer with ultraviolet light and lowering the potential of the first gate electrode, or by releasing charge from the first gate electrode.
-
29. A semiconductor device comprising a memory cell, the memory cell including a transistor and a capacitor,
wherein the transistor comprises a semiconductor layer, a gate electrode, a source electrode, and a drain electrode, wherein the semiconductor layer includes an oxide semiconductor material, wherein one of the source electrode and the drain electrode is electrically connected to a first electrode of the capacitor, and wherein data writing in the memory cell is done by raising a potential of the first electrode of the capacitor, or by storing charge in the first electrode of the capacitor, and wherein the data in the memory cell is erased by irradiating the semiconductor layer with ultraviolet light and lowering the potential of the first electrode of the capacitor, or by releasing the charge from the first electrode of the capacitor.
Specification