VOLTAGE COMPENSATION CIRCUIT, MULTI-LEVEL MEMORY DEVICE WITH THE SAME, AND VOLTAGE COMPENSATION METHOD FOR READING THE MULTI-LEVEL MEMORY DEVICE
First Claim
1. A memory device, comprising:
- at least one data cell, for storing multi-level data;
at least one reference cell, for providing a reference voltage;
a pair of bit lines, corresponding to the data cell, wherein the pair of bit lines comprises a data bit line and a reference bit line, and the data bit line is connected to the data cell; and
a compensation circuit, connected to the reference cell, the reference cell providing information of resistance varied along with time, and the compensation circuit generating a compensation voltage according to the information provided by the reference cell to apply to the reference voltage, thereby a result as the stored data of the data cell is sensed according to the reference voltage compensated by the compensation voltage.
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Abstract
A voltage compensation circuit, a multi-level memory device with the same, and a voltage compensation method for reading the multi-level memory device are provided. When a memory cell is read, a reference voltage applied to the memory device is adjusted according to variation of characteristics of a drift resistance of a reference cell. The increased value of the reference voltage (i.e. a voltage difference) corresponds to a resistance variation caused by a drift condition. The drift compensation mechanism is adaptive to a compensation circuit of a read driver of the memory device, which can compensate variation of the voltage level when data is read from the memory cell. When the resistance drift occurs, a drift amount is calculated and is added to the reference voltage, in order to avoid the error in judgement caused by the resistance drift when the stored data is read out.
35 Citations
18 Claims
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1. A memory device, comprising:
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at least one data cell, for storing multi-level data; at least one reference cell, for providing a reference voltage; a pair of bit lines, corresponding to the data cell, wherein the pair of bit lines comprises a data bit line and a reference bit line, and the data bit line is connected to the data cell; and a compensation circuit, connected to the reference cell, the reference cell providing information of resistance varied along with time, and the compensation circuit generating a compensation voltage according to the information provided by the reference cell to apply to the reference voltage, thereby a result as the stored data of the data cell is sensed according to the reference voltage compensated by the compensation voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 15)
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11. A voltage compensation circuit, adapted to a read device of a multi-level memory device, wherein the multi-level memory device comprises a plurality of data cells for storing multi-level data, wherein stored data of each of the data cells is read by comparing a reference voltage, and the read device comprises a plurality of reference cells, the voltage compensation circuit comprising:
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a first current mirror, having a source terminal coupled to one of the reference cells, and a mapping terminal coupled to a comparison terminal, to map a current flowing through the reference cell to the mapping terminal to generate a first current; a second current mirror, having a source terminal coupled to a reference voltage control switch, to generate a second current when the reference voltage control switch is turned on; and a third current mirror, having a source terminal coupled to a mapping terminal of the second current mirror to connect a third current generated by mapping the second current, and a mapping terminal coupled to the comparison terminal generating a fourth current for coupling to the comparison terminal, wherein the comparison terminal is used for controlling a voltage compensation switch, when the first current is less than the fourth current, the voltage compensation switch is turned on, and a voltage difference is compensated to a reference voltage corresponding to the data cell to be read. - View Dependent Claims (12, 13, 14)
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16. A voltage compensation method for reading a multi-level memory device, wherein the multi-level memory device comprises a plurality of data cells for storing multi-level data, wherein stored data of each of the data cells is read by comparing a reference voltage, and the read device comprises a plurality of reference cells, voltage compensation method for reading the multi-level memory device comprising:
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providing a power supply to activate the multi-level memory device to perform reading; selecting one of the data cells to read stored data, and correspondingly selecting one of the reference cells; mapping a current passing through the reference cell to generate a first current for coupling to a comparison terminal; turning on a reference voltage control switch to generate a second current when the reading is to be performed; and mapping the second current to generate a third current, and mapping the third current to generate a fourth current for coupling to the comparison terminal, wherein the comparison terminal is coupled to a voltage compensation switch, and when the first current is less than the fourth current, the voltage compensation switch is turned on, and a voltage difference is compensated to a reference voltage corresponding to the data cell to be read. - View Dependent Claims (17, 18)
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Specification