PROGRAMMING MEMORY WITH BIT LINE FLOATING TO REDUCE CHANNEL-TO-FLOATING GATE COUPLING

• US 20110122695A1
• Filed: 11/24/2009
• Published: 05/26/2011
• Est. Priority Date: 11/24/2009
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Li, Yan, Khandelwal, Anubhav
• Granted Patent: US 8,089,815 B2
• Time in Patent Office: Days
• US Class Current: 365/185.05
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

During programming of storage elements, channel-to-floating gate coupling effects are compensated to avoid increased programming speed and threshold voltage distribution widening. Programming speed can be adjusted by grounding the bit line of a selected storage element until it reaches a verify level which is below a target verify level of its target data state, after which the bit line is floated so that programming speed is slowed. The verify level which triggers the floating can be a target verify level of a data state that is one or more states below the target data state. Or, the verify level which triggers the floating can be an offset verify level of the target data state. An option is to raise the bit line voltage before it floats, to enter a slow programming mode, in which case there is a double slow down.

Claims

1. A storage system, comprising:

a set of storage elements, including at least one storage element which is to be programmed to a target data state;

a respective bit line associated with each storage element; and

one or more control circuits, the one or more control circuits, to perform a plurality of programming iterations of a programming operation for the set of storage elements;

(a) apply program pulses to the set of storage elements, with the respective bit line of the at least one storage element grounded, until the at least one storage element reaches a verify level which is below a target verify level of a target data state of the at least one storage element, and (b) in response to the at least one storage element reaching the verify level which is below the target verify level of the target data state of the at least one storage element, apply program pulses to the set of storage elements, with the respective bit line of the at least one storage element floated, until the at least one storage element reaches the target verify level of the target data state.

2. The storage system of claim 1, wherein:

in response to the at least one storage element reaching the verify level which is below the target verify level of the target data state of the at least one storage element, the one or more control circuits apply the program pulses to the set of storage elements, with the respective bit line of the at least one storage element floated after the respective bit line of the at least one storage element is raised to a level which is associated with a slow programming mode.

3. The storage system of claim 1, wherein:

the verify level which is below the target verify level of the target data state of the at least one storage element, is an offset verify level of the target data state of the at least one storage element.

4. The storage system of claim 1, wherein:

the verify level which is below the target verify level of the target data state, is a target verify level of a lower data state than the target data state of the at least one storage element.

5. The storage system of claim 4, wherein:

the lower data state is only one data state lower than the target data state of the at least one storage element.

6. The storage system of claim 4, wherein:

the lower data state is more than one data state lower than the target data state of the at least one storage element.

7. The storage system of claim 1, wherein:

the one or more control circuits lock out the at least one storage element from further programming when the at least one storage element reaches the target verify level of the target data state.

8. The storage system of claim 1, further comprising:

at least one latch which stores data associated with the at least one storage element, and which indicates whether the at least one storage element should be programmed with its respective bit line grounded or floated.

9. The storage system of claim 1, wherein:

the respective bit line of the at least one storage element, when floated, is coupled higher by a stepped up voltage on at least one adjacent unselected bit line, so that programming of the at least one storage element is slowed.

10. The storage system of claim 1, wherein:

the set of storage elements is in a memory array which includes a set of word lines; and

in connection with at least one of the program pulses in which the respective bit line of the at least one storage element is floated, the one or more control circuits raise a pass voltage on unselected word lines in the set of word lines before the respective bit line starts to float.

11. The storage system of claim 1, wherein:

the set of storage elements is in a memory array which includes a set of word lines; and

in connection with at least one of the program pulses in which the respective bit line of the at least one storage element is floated, the one or more control circuits raise a pass voltage on unselected word lines in the set of word lines after the respective bit line starts to float.

12. The storage system of claim 1, wherein:

the set of storage elements is in a memory array which includes a set of word lines;

a drain select transistor is provided between the at least one storage element and the respective bit line; and

in connection with at least one of the program pulses in which the respective bit line of the at least one storage element is floated, the one or more control circuits raise a pass voltage on unselected word lines in the set of word lines, and step up a gate voltage of the drain select transistor after a specified delay relative to when the pass voltage is raised.

13. The storage system of claim 1, wherein:

a drain select transistor is provided between the at least one storage element and the respective bit line; and

in connection with at least one of the program pulses in which the respective bit line of the at least one storage element is floated, the one or more control circuits step up a gate voltage of the drain select transistor after the respective bit line starts to float.

14. The storage system of claim 1, wherein:

a drain select transistor is provided between the at least one storage element and the respective bit line; and

in connection with at least one of the program pulses in which the respective bit line of the at least one storage element is floated, the one or more control circuits step up a gate voltage of the drain select transistor before the respective bit line starts to float.

15. A method for programming a set of storage elements in a storage system, each storage element is associated with a respective bit line, the method comprising:

performing a plurality of programming iterations of a programming operation for the set of storage elements, wherein the storage elements in the set include at least one storage element which is to be programmed to a target data state;

the performing the plurality of programming iterations includes;

applying program pulses to the set of storage elements, with the respective bit line of the at least one storage element grounded, until the at least one storage element reaches a verify level which is below a target verify level of a target data state of the at least one storage element; and

in response to the at least one storage element reaching the verify level which is below the target verify level of the target data state of the at least one storage element, applying program pulses to the set of storage elements, with the respective bit line of the at least one storage element floated, until the at least one storage element reaches the target verify level of the target data state.

16. The method of claim 15, wherein:

in response to the at least one storage element reaching the verify level which is below the target verify level of the target data state of the at least one storage element, the program pulses are applied to the set of storage elements, with the respective bit line of the at least one storage element floated after the respective bit line of the at least one storage element is raised to a level which is associated with a slow programming mode.

17. The method of claim 15, wherein:

the verify level which is below the target verify level of the target data state of the at least one storage element, is an offset verify level of the target data state of the at least one storage element.

18. The method of claim 15, wherein:

the verify level which is below the target verify level of the target data state, is a target verify level of a lower data state than the target data state of the at least one storage element.

19. The method of claim 18, wherein:

the lower data state is only one data state lower than the target data state of the at least one storage element.

20. The method of claim 18, wherein:

the lower data state is more than one data state lower than the target data state of the at least one storage element.

21. The method of claim 15, further comprising:

locking out the at least one storage element from further programming when the at least one storage element reaches the target verify level of the target data state.

22. The method of claim 15, further comprising:

providing latch data associated with the at least one storage element which indicates whether the at least one storage element should be programmed with its respective bit line grounded or floated.

23. The method of claim 15, wherein:

the respective bit line of the at least one storage element, when floated, is coupled higher by a stepped up voltage on at least one adjacent unselected bit line, thereby slowing programming of the at least one storage element.

24. The method of claim 15, wherein:

the set of storage elements is in a memory array which includes a set of word lines; and

in connection with at least one of the program pulses in which the respective bit line of the at least one storage element is floated, a pass voltage is raised on unselected word lines in the set of word lines before the respective bit line starts to float.

25. The method of claim 15, wherein:

the set of storage elements is in a memory array which includes a set of word lines; and

in connection with at least one of the program pulses in which the respective bit line of the at least one storage element is floated, a pass voltage is raised on unselected word lines in the set of word lines after the respective bit line starts to float.

26. The method of claim 15, wherein:

the set of storage elements is in a memory array which includes a set of word lines;

a drain select transistor is provided between the at least one storage element and the respective bit line; and

in connection with at least one of the program pulses in which the respective bit line of the at least one storage element is floated, a pass voltage is raised on unselected word lines in the set of word lines, and a gate voltage of the drain select transistor is stepped up after a specified delay relative to when the pass voltage is raised.

27. The method of claim 15, wherein:

a drain select transistor is provided between the at least one storage element and the respective bit line; and

in connection with at least one of the program pulses in which the respective bit line of the at least one storage element is floated, a gate voltage of the drain select transistor is stepped up after the respective bit line starts to float.

28. The method of claim 15, wherein:

a drain select transistor is provided between the at least one storage element and the respective bit line; and

in connection with at least one of the program pulses in which the respective bit line of the at least one storage element is floated, a gate voltage of the drain select transistor is stepped up before the respective bit line starts to float.

29. A storage system, comprising:

a set of storage elements, including at least one storage element which is to be programmed to a target data state;

a respective bit line associated with the at least one storage element; and

one or more control circuits, the one or more control circuits;

(a) program the set of storage elements, with the respective bit line grounded, until the at least one storage element reaches a verify level which is below a target verify level of a target data state of the at least one storage element, and (b) in response to the at least one storage element reaching the verify level which is below the target verify level of the target data state of the at least one storage element, continue programming the set of storage elements, with the respective bit line floated.

30. The storage system of claim 29, wherein:

in response to the at least one storage element reaching the verify level which is below the target verify level of the target data state of the at least one storage element, the one or more control circuits continue programming the set of storage elements, with the respective bit line floated after the respective bit line is raised to a level which is associated with a slow programming mode.

31. The storage system of claim 29, wherein:

the verify level which is below the target verify level of the target data state of the at least one storage element, is an offset verify level of the target data state of the at least one storage element.

32. The storage system of claim 29, wherein:

the verify level which is below the target verify level of the target data state, is a target verify level of a lower data state than the target data state of the at least one storage element.