METHOD AND SYSTEM FOR ANALYZING AND QUALIFYING ROUTES IN PACKET NETWORKS

• US 20110122775A1
• Filed: 07/02/2010
• Published: 05/26/2011
• Est. Priority Date: 11/20/2009
• Status: Active Grant

• Current Assignee: Microsemi Frequency And Time Corporation
• Original Assignee: Symmetricom Incorporated (Microchip Technology Incorporated)
• Inventors: ZAMPETTI, George P., SHENOI, Kishan
• Granted Patent: US 8,427,963 B2
• Time in Patent Office: Days
• US Class Current: 370/242
• CPC Class Codes: H04J 3/0641 Change of the master or reference, e.g. take-over or failure of the master
• CPC Class Codes: H04J 3/0682 by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
• CPC Class Codes: H04L 41/082 the condition being updates or upgrades of network functionality
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00
• CPC Class Codes: H04L 45/121 by minimising delays

Abstract

Routes of a packet network are analyzed according to various transit delay metrics. Preferred packet network routes are selected between source and destination based on these metrics. In packet networks employing boundary clocks and transparent clocks, faulty boundary clocks and faulty transparent clocks are identified using the metrics.

Claims

1. A method of routing a timing packet between a master clock and a slave clock of a packet network, comprising the steps of:

transmitting a first set of timing packets between the master clock and the slave clock along a first path;

evaluating a transit delay characteristic of the first path based on timing information contained in the timing packets of the first set;

transmitting a second set of timing packets between the master clock and the slave clock along a second path;

evaluating a transit delay characteristic of the second path based on timing information contained in the timing packets of the second set; and

controlling future timing packets to be transmitted between the master clock and the slave clock along the path that has a better transit delay characteristic.

2. The method according to claim 1, wherein the step of controlling includes the step of:

updating routing tables at nodes that are included in the path that has the better transit delay characteristic.

3. The method according to claim 1, wherein the step of controlling includes the step of:

appending a multi-protocol label to the future timing packets,

wherein the future timing packets are routed along the path that has the better transit delay characteristic based on the multi-protocol label.

4. The method according to claim 1, wherein the timing information contained in the timing packets include a transmit time stamp and a receive time stamp.

5. The method according to claim 1, wherein the timing information contained in the timing packets include a transmit time stamp of the master clock, a receive time stamp of the slave clock, a transmit time stamp of the slave clock, and a receive time stamp of the master clock.

6. The method according to claim 1, wherein the first path includes at least one transparent clock and the step of evaluating the transit delay characteristics of the first path and the second path ignores timing data inserted into the timing packets by the transparent clock.

7. The method according to claim 1, further comprising:

correcting the slave clock based on the future timing packets.

8. A method of selecting a master clock for use in correcting a slave clock, comprising:

transmitting a first set of timing packets between a first master clock and the slave clock along a first path;

evaluating a transit delay characteristic of the first path based on timing information contained in the timing packets of the first set;

transmitting a second set of timing packets between a second master clock and the slave clock along a second path;

evaluating a transit delay characteristic of the second path based on timing information contained in the timing packets of the second set; and

selecting one of the first master clock and the second master clock for use in correcting the slave clock based on the transit delay characteristics of the first path and the second path.

9. The method according to claim 8, wherein the master clock associated with the path that has the better transit delay characteristic is selected.

10. The method according to claim 8, wherein the first and second paths traverse nodes of a packet network, and the slave clock has a single physical interface an end node of the packet network and multiple virtual interfaces to the end node of the packet network.

11. The method according to claim 10, wherein the packets transmitted along the first path travel across a first virtual interface to/from the end node and the packets transmitted along the second path travel across a second virtual interface to/from the end node.

12. The method according to claim 8, further comprising:

correcting a frequency of the slave clock based on the timing packets received from said one of the first master clock and the second master clock and the timing information in the timing packets,

wherein the timing information contained in the timing packets include a transmit time stamp of the master clock and a receive time stamp of the slave clock.

13. The method according to claim 8, further comprising:

correcting a frequency of the slave clock based on the timing packets received from said one of the first master clock and the second master clock and the timing information in the timing packets,

wherein the timing information contained in the timing packets include a transmit time stamp of the slave clock and a receive time stamp of the master clock.

14. The method according to claim 8, further comprising:

correcting time and frequency of the slave clock based on the timing packets received from said one of the first master clock and the second master clock and the timing information in the timing packets,

wherein the timing information contained in the timing packets include a transmit time stamp of the master clock, a receive time stamp of the slave clock, a transmit time stamp of the slave clock, and a receive time stamp of the master clock.

15. A computer network comprising:

one or more master clocks;

one or more slave clocks;

a plurality of network elements between the master clocks and the slave clocks; and

a network management system coupled to each of the master clocks, the slave clocks, and the network elements, the network management system being configured to route timing packets from one of the master clocks to each of the slave clocks along each slave clock'"'"'s respective preferential path.

16. The computer network according to claim 15, wherein the network management system is further configured to update routing tables of the network elements to route the timing packets along each slave clock'"'"'s respective preferential path.

17. The computer network according to claim 15, wherein the network management system is further configured to direct the network elements to append multi-protocol labels to the timing packets to cause the timing packets to be routed along each slave clock'"'"'s respective preferential path.

18. The computer network according to claim 15, wherein the network management system is further configured to evaluate a first path and a second path to determine a congested state in a third path.

19. The computer network according to claim 15, wherein the network management system is further configured to evaluate a first path and a second path to determine a faulty transparent clock.

20. The computer network according to claim 15, wherein the network management system is further configured to evaluate a first path and a second path to determine a faulty boundary clock.