Method of Manufacturing Semiconductor Device

• US 20110124173A1
• Filed: 11/12/2010
• Published: 05/26/2011
• Est. Priority Date: 11/25/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Sung-Hwan, Satoru, Yamada
• Granted Patent: US 8,043,923 B2
• Time in Patent Office: Days
• US Class Current: 438/305
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

Methods of manufacturing a semiconductor device include forming a gate electrode on a semiconductor substrate, forming spacers on side walls of the gate electrode, and doping impurities into the semiconductor substrate on both sides of the spacers to form highly doped impurity regions. The spacers are selectively etched to expose portions of the semiconductor substrate, and more lightly doped impurity regions are formed in the semiconductor substrate between the highly doped impurity regions and the gate electrode.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a gate electrode on a semiconductor substrate, the gate electrode having opposing side walls;

forming spacers on the side walls of the gate electrode;

doping impurities into the semiconductor substrate on opposing sides of the spacers to form highly doped impurity regions having a first concentration of doping impurities in the semiconductor substrate;

selectively removing the spacers to expose portions of the semiconductor substrate between the highly doped impurity regions and the gate electrode; and

forming lightly doped impurity regions in the exposed portions of the semiconductor substrate between the highly doped impurity regions and the gate electrode, the lightly doped impurity regions having a second concentration of impurities that is lower than the first concentration of impurities.

2. The method of claim 1, further comprising forming side wall oxide spacers by oxidizing the side walls of the gate electrode.

3. The method of claim 1, wherein the spacers comprise silicon oxide.

4. The method of claim 1, further comprising forming an offset spacer layer on the side walls of the gate electrode and on an upper surface of the semiconductor substrate, wherein the offset spacer layer is on the semiconductor substrate between the spacers and the gate electrode;

and

anisotropically etching the offset spacer layer to form an offset spacer.

5. The method of claim 4, wherein the offset spacer layer comprises silicon nitride.

6. The method of claim 4, wherein forming the spacers comprises

forming a spacer layer on the offset spacer layer;

and

anisotropically etching the spacer layer.

7. A method of manufacturing a semiconductor device, comprising:

forming a gate electrode on a semiconductor substrate in a peripheral region of the semiconductor substrate, the semiconductor substrate being divided into a cell region and the peripheral region, the gate electrode having opposing side walls;

forming spacers on the side walls of the gate electrode;

doping impurities into the semiconductor substrate in the peripheral region on opposing sides of the spacers to form highly doped impurity regions having a first concentration of doping impurities in the semiconductor substrate;

removing the spacers from the side walls of the gate electrode; and

forming lightly doped impurity regions in the substrate on the opposing sides of the gate electrode, wherein the lightly doped impurity regions are between the highly doped impurity regions and the gate electrode, the lightly doped impurity regions having a second concentration of impurities that is lower than the first concentration of impurities.

8. The method of claim 7, further comprising forming side wall oxide spacers on the gate electrode by oxidizing the side walls of the gate electrode.

9. The method of claim 7, wherein the spacers comprise silicon oxide.

10. The method of claim 7, further comprising:

forming an offset spacer layer on an upper surface of the substrate and on the side walls of the gate electrode; and

anisotropically etching the offset spacer layer to form offset spacers on the side walls of the gate electrode.

11. The method of claim 10, wherein the offset spacer layer comprises silicon nitride.

12. The method of claim 10, wherein the spacers are formed by:

forming a spacer layer on the offset spacer layer; and

anisotropically etching the spacer layer.

13. The method of claim 7, wherein a conductive layer pattern is formed as a bit line in the cell region during formation of the gate electrode in the peripheral region.

14. The method of claim 13, wherein forming the spacers comprises:

forming a spacer layer on the offset spacer layer; and

anisotropically etching the spacer layer to form first spacers on side walls of the gate electrode and second spacers on side walls of the conductive layer pattern.

15. The method of claim 16, wherein the second spacers on the side walls of the conductive layer pattern in the cell region are removed during removal of the first spacers from the side walls of the gate electrode.

16. The method of claim 12, wherein portions of the spacer layer formed in the cell region are removed during anisotropic etching of the spacer layer.

17. The method of claim 7, further comprising forming a photoresist layer pattern on the cell region after forming the spacers.

18. The method of claim 7, further comprising heat treating the substrate to activate the high concentration impurities after forming the highly doped impurity regions.

19. The method of claim 18, wherein the spacers comprise first spacers, and wherein a second spacer is formed on the side wall of the conductive layer pattern in the cell region during anisotropic etching for forming the offset spacer on the side wall of the gate electrode.

20. A method of manufacturing a semiconductor device, comprising:

forming a gate electrode on a semiconductor substrate;

forming a spacer on a side wall of the gate electrode;

doping impurities into the substrate adjacent the spacer to form a highly doped impurity region having a first concentration of doping impurities;

selectively removing the spacer to expose a portion of the semiconductor substrate between the highly doped impurity region and the gate electrode; and

forming a lightly doped impurity region in the exposed portion of the substrate between the highly doped impurity region and the gate electrode, the lightly doped impurity region having a second concentration of impurities that is lower than the first concentration of impurities.