SWITCH MODE VOLTAGE RECTIFIER, RF ENERGY CONVERSION AND WIRELESS POWER SUPPLIES

• US 20110124310A1
• Filed: 11/18/2010
• Published: 05/26/2011
• Est. Priority Date: 11/18/2009
• Status: Active Grant

• Current Assignee: Regents of the University of California (University of California)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Theilmann, Paul, Asbeck, Peter
• Granted Patent: US 8,415,837 B2
• Time in Patent Office: Days
• US Class Current: 455/343.1
• CPC Class Codes: H02J 50/20 using microwaves or radio frequency waves
• CPC Class Codes: H02M 7/219 in a bridge configuration
• CPC Class Codes: H02M 7/2195 the switches being synchronously commutated at the same frequency of the AC input voltage
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

Embodiments of the present invention provide cross-coupled rectifiers that use near zero-threshold transistors in a switching topology, but provide a topology that avoids reverse conduction problems. Importantly, preferred embodiment rectifiers of the invention only provide a slightly increased on-resistance in each branch, while providing both very high operating efficiency and very low turn-on voltage. An embodiment of the invention is a voltage rectifier for the conversion of RF energy into DC voltage with a turn-on threshold voltages approaching 0V.

Claims

1. A very lower power RF voltage rectifier, comprising:

differential positive and negative inputs;

a load; and

a switching mode CMOS gate cross-connected bridge connecting said differential input to said load, said CMOS gate cross-connected bridge comprising,

a first series path from the positive input through a first near zero threshold PMOS switching transistor and first near zero-threshold NMOS blocking transistor to one of ground or a load;

a second series path from the negative input through a first near zero-threshold NMOS switching transistor and second near zero-threshold PMOS blocking transistor to the other of said load and said ground;

a third series path from between the negative input through a third near zero-threshold PMOS switching transistor and a third near zero-threshold NMOS blocking transistor to said one of ground or a load; and

a fourth series path from the positive input through a fourth near zero-threshold NMOS switching transistor and fourth near zero-threshold PMOS blocking transistor to the other of said load and said ground.

2. The rectifier of claim 1, wherein said differential positive and negative inputs are connected to an RF antenna.

3. The rectifier of claim 2, wherein said load comprises a DC biomedical device.

4. The rectifier of claim 2, wherein said load comprises a DC RFID circuit.

5. A multi-stage rectifier comprises a series of rectifiers of claim 1 capacitively coupled between said inputs and said load.

6. The rectifier of claim 1, wherein said switching and blocking transistors comprise silicon on insulator near zero-threshold transistors.

7. The rectifier of claim 6, wherein said switching and blocking transistors comprise silicon on sapphire near zero-threshold transistors.

8. The rectifier of claim 1, wherein said switching and blocking transistors comprise triple well near zero-threshold transistors.

9. The rectifier of claim 1, wherein said switching and blocking transistors comprise programmable threshold near zero-threshold transistors.

10. The rectifier of claim 1, wherein the widths of NMOS and PMOS transistors in said CMOS cross-connected bride is set for equal on-resistance.

11. A very lower power RF voltage rectifier, comprising:

a CMOS gate cross-connected switching mode bridge having near zero-threshold devices to convert RF signals to DC energy; and

blocking transistor means for blocking shoot through current losses.

12. A very lower power RF voltage rectifier, comprising:

a differential input connected to a gate of a first near zero-threshold PMOS switching transistor, a gate of a second near zero-threshold NMOS switching transistor, a gate of a third near-zero threshold NMOS blocking transistor, a source of a third near-zero threshold PMOS switching transistor, a gate of a fourth near zero-threshold PMOS blocking transistor, and a source of a fourth near zero-threshold NMOS switching transistor;

an opposite differential input connect to a source of said first near zero-threshold PMOS switching transistor, a gate of a first near-zero threshold NMOS blocking transistor, a source of said second near zero-threshold NMOS switching transistor, a gate of a second near-zero threshold PMOS blocking transistor, a gate of said third near zero-threshold PMOS switching transistor, and a gate of said fourth near zero-threshold NMOS switching transistor;

sources of said first and third blocking transistors being connected to each other or to each other and a load;

sources of said second and further blocking transistors being connected to each other or to each other and a load; and

drains of respective ones of said first through fourth switching transistors being connect to drains of said first through further blocking transistors.

13. The rectifier of claim 12, wherein said switching and blocking transistors comprise silicon on insulator near zero-threshold transistors.

14. The rectifier of claim 13, wherein said switching and blocking transistors comprise silicon on sapphire near zero-threshold transistors.

15. The rectifier of claim 12, wherein said switching and blocking transistors comprise triple well near zero-threshold transistors.

16. The rectifier of claim 12, wherein said switching and blocking transistors comprise programmable threshold near zero-threshold transistors.