FLASH MEMORY ORGANIZATION FOR REDUCED FAILURE RATE

• US 20110125953A1
• Filed: 11/23/2009
• Published: 05/26/2011
• Est. Priority Date: 11/23/2009
• Status: Active Grant

• Current Assignee: AgigA Tech Incorporated (Infineon Technologies AG)
• Original Assignee: AgigA Tech Incorporated (Infineon Technologies AG)
• Inventors: Sartore, Ronald H.
• Granted Patent: US 9,244,836 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0646 Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A memory system includes logic to distribute bits of a data word from a first memory across multiple pages of a flash memory.

Claims

1. A memory system comprising:

logic to distribute bits of a data word from a first memory across multiple pages of a flash memory.

2. The memory system of claim 1, the first memory is random access memory (RAM), each data word of the RAM is distributed over multiple flash pages of multiple flash memory devices.

3. The memory system of claim 1, a number of flash pages over which the data word is distributed is equal to a number of data bits in the data word.

4. The memory system of claim 1, wherein an error correcting code (ECC) of the data word is also distributed over multiple flash pages.

5. The memory system of claim 4, the number of flash pages over which the ECC is distributed is equal to a number of data bits in the ECC.

6. The memory system of claim 1, the number of data bits in each flash memory page is between one and five.

7. The memory system of claim 1, comprising logic to separately process data words from different RAM devices such that some RAM devices remain in a low power state while data words from other RAM devices are being distributed across multiple flash memory pages.

8. The memory system of claim 1, wherein each flash page stores one bit from a particular bit position of multiple data words of the first memory.