INTERLEAVING APPARATUSES AND MEMORY CONTROLLERS HAVING THE SAME

• US 20110125975A1
• Filed: 11/12/2010
• Published: 05/26/2011
• Est. Priority Date: 11/23/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Eun, Hee-Seok, Kim, Yong-June, KIM, Jaehong, Lee, Ki-Jun
• Granted Patent: US 8,812,942 B2
• Time in Patent Office: Days
• US Class Current: 711/157
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices

Abstract

An interleaving apparatus may include a first buffer unit configured to buffer input data in units having a size of a sector to generate sector unit data, an encoding unit configured to encode the sector unit data and generate a plurality of parity codes based on the encoding, a second buffer unit configured to interleave the sector unit data and the parity codes and generate interleaving data based on the interleaving, the second buffer unit including a plurality of output buffers configured to store the interleaving data, and an output unit configured to output the interleaving data.

Claims

1. An interleaving apparatus, comprising:

a first buffer unit configured to buffer input data in units having a size of a sector to generate sector unit data;

an encoding unit configured to encode the sector unit data and generate a plurality of parity codes based on the encoding;

a second buffer unit configured to interleave the sector unit data and the parity codes and generate interleaving data based on the interleaving, the second buffer unit including a plurality of output buffers configured to store the interleaving data; and

an output unit configured to output the interleaving data.

2. The interleaving apparatus of claim 1, wherein the first buffer unit includes an input buffer, a size of the input buffer being the sector.

3. The interleaving apparatus of claim 2, wherein sizes of the plurality of output buffers are between the sector and a page.

4. The interleaving apparatus of claim 1, wherein the second buffer unit is configured to divide the sector unit data and the parity codes into a plurality of data groups and interleave the plurality of data groups.

5. The interleaving apparatus of claim 4, wherein the second buffer unit is configured to divide the sector unit data and the parity codes into a first data group and a second data group, divide the plurality of output buffers into a first buffer group and a second buffer group, interleave the first data group into the first buffer group, and interleave the second data group into the second buffer group.

6. The interleaving apparatus of claim 1, wherein the second buffer unit is configured to divide the sector unit data and the parity codes into a plurality of data groups, interleave at least one of the plurality of data groups and sequentially store at least another of the plurality of data groups.

7. The interleaving apparatus of claim 6, wherein the second buffer unit is configured to divide the sector unit data and the parity codes into a first data group and a second data group, divide the plurality of output buffers into a first buffer group and a second buffer group, interleave the first data group into the first buffer group, and sequentially store the second data group in the second buffer group.

8. The interleaving apparatus of claim 1, wherein the second buffer unit is configured to divide the sector unit data and the parity codes into a plurality of data groups, interleave at least one of the plurality of data groups into the output buffers, and directly output at least another of the plurality data groups to at least one memory device.

9. The interleaving apparatus of claim 8, wherein the second buffer unit is configured to divide the sector unit data and the parity codes into a first data group and a second data group, interleave the first data group into the output buffers, and directly output the second data group to the at least one memory device.

10. The interleaving apparatus of claim 1, wherein the output unit is configured to encode the interleaving data and output encoded interleaving data.

11. A memory controller, comprising:

a write unit configured to receive write commands and write addresses, buffer input data output from a host device in units having a size of a sector to generate sector unit data, interleave the sector unit data, generate interleaving data based on the interleaving, and to write the interleaving data into at least one memory device in response to the write commands and write addresses; and

a read unit configured to receive read commands and read addresses, read read data from the at least one memory device in response to the read commands and read addresses, generate output data based on the read data, and output the output data to the host device.

12. The memory controller of claim 11, wherein the memory controller further comprises:

a central processing unit configured to control the write unit and the read unit;

a host interface configured to receive the input data from the host device and output the output data to the host device; and

a memory interface configured to output the interleaving data and receive the read data from the at least one memory device.

13. The memory controller of claim 11, wherein the write unit comprises:

a first buffer unit configured to buffer the input data and generate the sector unit data based on the input data;

an encoding unit configured to encode the sector unit data and generate a plurality of parity codes based on the encoding;

a second buffer unit configured to interleave the sector unit data and the parity codes and generate the interleaving data, the second buffer including a plurality of output buffers configured to store the interleaving data; and

a memory output unit configured to output the interleaving data to the at least one memory device.

14. The memory controller of claim 13, wherein the memory output unit is configured to encode the interleaving data and output the encoded interleaving data to the at least one memory device.

15. The memory controller of claim 13, wherein the read unit comprises:

a third buffer unit configured to store the read data;

a decoding unit configured to decode the read data and generate the output data based on the decoding; and

a host output unit configured to output the output data to the host device.

16. The memory controller of claim 13, wherein the second buffer unit is configured to divide the sector unit data and the parity codes into a plurality of data groups and interleave the plurality of data groups.

17. The memory controller of claim 13, wherein the second buffer unit is configured to divide the sector unit data and the parity codes into a plurality of data groups, interleave at least one of the plurality of data groups and sequentially store at least another of the plurality of data groups.

18. The memory controller of claim 13, wherein the second buffer unit is configured to divide the sector unit data and the parity codes into a plurality of data groups, interleave at least one of the plurality of data groups into the output buffers, and directly output at least another of the plurality of data groups to the at least one memory device.

19. A system comprising:

a memory controller including,

a write unit configured to receive write commands and write addresses, buffer input data output from a host device in units having a size of a sector to generate sector unit data, interleave the sector unit data, generate interleaving data based on the interleaving, and to write the interleaving data into at least one memory device in response to the write commands and write addresses, and

a read unit configured to receive read commands and read addresses, read read data from the at least one memory device in response to the read commands and read addresses, generate output data based on the read data, and output the output data to the host device;

the host device configured to output the input data and receive the output data; and

the at least one memory device configured to receive the interleaving data.

20. The memory controller of claim 19, wherein the memory controller is in one of the host device and the at least one memory device.