Distributed Multi-Core Memory Initialization
First Claim
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1. A method for causing a plurality of processing nodes to perform a boot process task, comprising:
- dividing a boot process task into a plurality of boot process sub-tasks at a control processing node,distributing the plurality of boot process sub-tasks amongst the plurality of processing nodes so that each boot process sub-task has a corresponding processing node,executing each boot process sub-task at the corresponding processing node to generate a sub-task result, andcombining sub-task results from the plurality of processing nodes at the control processing node, wherein the plurality of boot process sub-tasks may be executed in parallel or in sequence at the plurality of processing nodes.
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Abstract
In a system having a plurality of processing nodes, a control node divides a task into a plurality of sub-tasks, and assigns the sub-tasks to one or more additional processing nodes which execute the assigned sub-tasks and return the results to the control node, thereby enabling a plurality of processing nodes to efficiently and quickly perform memory initialization and test of all assigned sub-tasks.
48 Citations
20 Claims
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1. A method for causing a plurality of processing nodes to perform a boot process task, comprising:
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dividing a boot process task into a plurality of boot process sub-tasks at a control processing node, distributing the plurality of boot process sub-tasks amongst the plurality of processing nodes so that each boot process sub-task has a corresponding processing node, executing each boot process sub-task at the corresponding processing node to generate a sub-task result, and combining sub-task results from the plurality of processing nodes at the control processing node, wherein the plurality of boot process sub-tasks may be executed in parallel or in sequence at the plurality of processing nodes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A computer system comprising:
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a system memory; and a plurality of processing nodes, each of the processing nodes comprising a processor core, a communication interface to at least one other of the plurality of processing nodes, and a memory controller for managing data flow to and from the system memory, the plurality of processing nodes comprising a master processing node and one or more execution processing nodes, where the master processing node is configured to perform a memory initialization task on the system memory by dividing the memory initialization task into a plurality of memory initialization sub-tasks and assigning the plurality of memory initialization sub-tasks to the one or more execution processing nodes so that each assigned memory initialization sub-task has a corresponding execution processing node, wherein the plurality of memory initialization sub-tasks may be executed in parallel or in sequence at the one or more execution processing nodes. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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18. A computer system comprising:
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a memory array; and a plurality of processing nodes, each of the processing nodes comprising a processor, a memory controller for communicating with the memory array, and a communication interface to at least one other of the plurality of processing nodes; wherein one of the plurality of processing nodes divides a memory initialization task into a plurality of sub-tasks and assigns the plurality of sub-tasks to the plurality of processing nodes; and wherein each of the plurality of processing nodes can obtain information from any portion of the memory array while executing assigned sub-tasks and returns sub-task execution results to the one of the plurality of processing nodes, thereby enabling the plurality of processing nodes to efficiently and quickly perform memory initialization of the memory array. - View Dependent Claims (19, 20)
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Specification