SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS AND METHOD OF FORMING THE STRUCTURE

• US 20110127529A1
• Filed: 11/30/2009
• Published: 06/02/2011
• Est. Priority Date: 11/30/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Botula, Alan B., Levy, Max G., Phelps, Richard A., Ellis-Monaghan, John J., Slinkman, James A., Joseph, Alvin J., Wolf, Randy L.
• Granted Patent: US 8,471,340 B2
• Time in Patent Office: Days
• US Class Current: 257/49
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence

Abstract

Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.

Claims

1. A semiconductor structure comprise:

a semiconductor substrate having a given conductivity type, a first surface and a second surface above said first surface, said semiconductor substrate comprising;

a first portion adjacent to said first surface and comprising, in a first concentration, a dopant having said given conductivity type; and

a second portion extending from said first portion to said second surface, said second portion comprising, in a second concentration greater than said first concentration, any of the following;

a same dopant as in said first portion,

a different dopant than in said first portion, said different dopant having said given conductivity type, and

a combination of said same dopant and said different dopant; and

an insulator layer adjacent to said second surface.

2. The semiconductor structure of claim 1, wherein a resistance of said first portion is at least 10 ohm-centimeters (Ω

-cm) and a sheet resistance of said second portion is at least 1×

10³ ohms per square (Ω

/□

).

3. The semiconductor structure of claim 1, said second portion comprising an implant region.

4. The semiconductor structure of claim 1, said first portion comprising a first semiconductor layer and said second portion comprising a second semiconductor layer on said first semiconductor layer.

5. The semiconductor structure of claim 4, said first semiconductor layer comprising a silicon layer and said second semiconductor layer comprising any of a second silicon layer and a polysilicon layer.

6. The semiconductor structure of claim 1, further comprising a device layer on said insulator layer.

7. The semiconductor structure of claim 1, said second portion suppressing formation of a parasitic inversion charge layer at said second surface and, thereby reducing harmonic behavior.

8. A semiconductor structure comprise:

a semiconductor substrate having a given conductivity type, a first surface and a second surface above said first surface, said semiconductor substrate comprising;

a first portion adjacent to said first surface and comprising, in a first concentration, a dopant having said given conductivity type; and

a second portion extending from said first portion to said second surface and comprising

a plurality of microcavities; and

;

in a second concentration greater than said first concentration, any of the following;

a same dopant as in said first portion,

a different dopant than in said first portion, said different dopant having said given conductivity type, and

a combination of said same dopant and said different dopant; and

an insulator layer adjacent to said second surface.

9. The semiconductor structure of claim 8, wherein a resistance of said first portion is at least 10 ohm-centimeters (Ω

-cm) and a sheet resistance of said second portion is at least 1×

10³ ohms per square (Ω

/□

).

10. The semiconductor structure of claim 8, said second portion comprising an implant region.

11. The semiconductor structure of claim 8, said first portion comprising a first semiconductor layer and said second portion comprising a second semiconductor layer on said first semiconductor layer.

12. The semiconductor structure of claim 11, said first semiconductor layer comprising a silicon layer and said second semiconductor layer comprising one of a second silicon layer and a polysilicon layer.

13. The semiconductor structure of claim 8, further comprising a device layer on said insulator layer.

14. The semiconductor structure of claim 8, said second portion suppressing formation of a parasitic inversion charge layer at said first surface and, thereby reducing harmonic behavior.

15. A method of forming a semiconductor structure comprise:

forming a semiconductor substrate having a given conductivity type and a first surface;

forming an insulator layer on a second surface of said substrate above said first surface; and

performing additional processing so as to form in said semiconductor substrate;

a first portion adjacent to said first surface and comprising, in a first concentration, a dopant having said given conductivity type; and

a second portion extending from said first portion to said second surface and comprising, in a second concentration greater than said first concentration, one of the following;

a same dopant as in said first portion,

a different dopant than in said first portion, said different dopant having said given conductivity type, and

a combination of said same dopant and said different dopant.

16. The method of claim 15, further comprising:

implanting gas ions into said second portion; and

,

heating said semiconductor substrate so as to create, from said gas ions, micro-cavities in said second portion.

17. The method of claim 15, said additional processing being performed such that a resistance of said first portion is at least 10 ohm-centimeters (Ω

-cm) and a sheet resistance of said second portion is at least 1×

10³ ohms per square (Ω

/□

).

18. The method of claim 15 further comprising forming a device layer on said insulator layer.

19. The method of claim 15, said additional processing being performed such that said second portion suppresses formation of a parasitic inversion charge layer at said first surface and, thereby reduces harmonic behavior.

20. A method of forming a semiconductor structure comprise:

forming a semiconductor substrate having a first surface and, during said forming of said semiconductor substrate, doping said semiconductor substrate with a first concentration of a dopant having a given conductivity type;

forming an insulator layer on a second surface of said substrate above said first surface; and

implanting one of said dopant and a different dopant having said given conductivity type into said semiconductor substrate to a predetermined depth below said second surface such that, after said implanting, said semiconductor substrate comprises;

a first portion adjacent to said first surface and comprising, in said first concentration, said dopant; and

a second portion extending from said predetermined depth to said second surface and comprising, in a second concentration higher than said first concentration, one of the following;

said dopant and a combination of said dopant and said different dopant.

21. The method of claim 20, further comprising:

implanting gas ions into said second portion; and

,

heating said semiconductor substrate so as to create, from said gas ions, micro-cavities in said second portion.

22. The method of claim 20, wherein a resistance of said first portion is at least 10 ohm-centimeters (Ω

-cm) and a sheet resistance of said second portion is at least 1×

10³ ohms per square (Ω

/□

).

23. The method of claim 20 further comprising forming a device layer on said insulator layer.

24. The method of claim 20, said implanting being performed such that said second portion suppresses formation of a parasitic inversion charge layer at said first surface and, thereby reduces harmonic behavior.

25. A method of forming a semiconductor structure comprise:

forming a semiconductor substrate, said forming of said semiconductor substrate comprising;

forming a first portion and, during said forming of said first portion, doping said first portion with a first concentration of a dopant having a given conductivity type; and

forming a second portion on said first portion and, during said forming of said portion, doping said second portion with a second concentration of one of said dopant and a different dopant having said given conductivity type, said second concentration being greater than said first concentration; and

forming an insulator layer on said second portion.