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ESD Induced Artifact Reduction Design for a Thin Film Transistor Image Sensor Array

  • US 20110127534A1
  • Filed: 02/09/2011
  • Published: 06/02/2011
  • Est. Priority Date: 10/14/2008
  • Status: Abandoned Application
First Claim
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1. An image sensor array having reduced potential defects from electrostatic discharge events during fabrication, comprisinga substrate;

  • at least one pixel disposed on the substrate, the pixel including a switching transistor and a photo-sensitive cell, the switching transistor having a transistor electrode, and the photo-sensitive cell having a cell electrode;

    a dielectric interlayer disposed over the switching transistor and the photo-sensitive cell; and

    a connecting line disposed on the dielectric interlayer, the connecting line connected to a via through the dielectric interlayer to contact one of the transistor electrode and the cell electrode,wherein a portion of the connecting line disposed on the dielectric interlayer comprises a second conductive layer disposed directly on a first conductive layer,wherein a portion of the via contacting the electrode through the dielectric interlayer comprises the second conductive layer without the first conductive layer, andwhereby the pixels of the image sensor array are substantially protected from electrostatic discharge events during fabrication by the presence of the first conductive layer deposited over the dielectric interlayer.

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