SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

• US 20110127587A1
• Filed: 07/09/2010
• Published: 06/02/2011
• Est. Priority Date: 11/27/2009
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: YANG, Hee Jung
• Granted Patent: US 8,288,801 B2
• Time in Patent Office: Days
• US Class Current: 257/263
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/66901 with a PN homojunction gate
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence

Abstract

The present invention relates to a semiconductor device, which includes a junction region formed in an active area of a semiconductor substrate; a trench defining a buried gate predetermined area within the semiconductor substrate; a gate electrode buried in an lower portion of the trench; an ion implantation region formed in a sidewall of the trench; and a capping insulation layer formed in an upper portion of the gate electrode.

Claims

1. A semiconductor device, comprising:

a trench defined in an active region of a semiconductor substrate;

a junction region formed in the active region adjacent to of the trench and proximate an upper portion of the trench;

a gate electrode defined within an lower portion of the trench; and

an ion implantation region formed in a sidewall of the trench.

2. The semiconductor device of claim 1, wherein the ion implantation region is configured to be overlapped with an upper portion of side wall of the gate electrode.

3. The semiconductor device of claim 1, wherein the ion implantation region is configured to be overlapped with the junction region.

4. The semiconductor device of claim 1, wherein the ion implantation region is configured to be overlapped with an upper portion of side wall of the gate electrode, and be overlapped with the junction region.

5. A method of manufacturing a semiconductor device, the method comprising:

forming a trench defining a buried gate within a semiconductor substrate;

filling conductive material within the trench;

removing an upper portion of the conductive material to define a gate electrode within a lower portion of the trench; and

implanting ions on a sidewall of the trench to define an implantation region.

6. The method of claim 5, before forming the trench, further comprising forming a junction region within the semiconductor substrate.

7. The method of claim 5, wherein the implanting step is performed to be overlapped with an upper portion of a side wall of the gate electrode.

8. The method of claim 5, wherein the implanting step is performed to be overlapped with the junction region.

9. The method of claim 5, wherein the implanting step is performed to be overlapped with an upper portion of a side wall of the gate electrode and the junction region.

10. The method of claim 5, wherein the implanting step is performed by a slant ion implantation process.

11. The method of claim 10, wherein the slant ion implantation process is performed at an angle of 0.1 degree to 45 degrees.

12. The method of claim 5, wherein the implanting step is preformed by a plasma ion implantation process.

16. The method of claim 11, wherein the slant ion implantation process has a slant angle of 0.1 degree to 45 degrees.

17. The method of claim 12, wherein forming the ion implantation region comprises performing a plasma ion implantation process.

13. A method of manufacturing a semiconductor device, the method comprising:

forming a trench defining a buried gate within a semiconductor substrate;

implanting ions on a sidewall of the trench to define an implantation region;

filling conductive material within the trench; and

removing an upper portion of the conductive material to define a gate electrode within a lower portion of the trench.

14. The method of claim 13, before forming the trench within the semiconductor substrate, further comprising forming a junction region within the semiconductor substrate.

15. The method of claim 13, wherein the implanting step is performed by a slant ion implantation process.