SEMICONDUCTOR STRUCTURE HAIVNG A METAL GATE AND METHOD OF FORMING THE SAME

• US 20110127589A1
• Filed: 12/02/2009
• Published: 06/02/2011
• Est. Priority Date: 12/02/2009
• Status: Active Grant

• Current Assignee: Marlin Semiconductor Limited (f/k/a Sandyford Semiconductor Limited) (Vector Capital Corporation)
• Original Assignee: United Microelectronics Corporation
• Inventors: Ho, Nien-Ting, Chen, Yi-Wei, Lin, Chin-Fu, Huang, Chien-Chung
• Granted Patent: US 9,048,254 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/2633 for etching, e.g. sputteretching
• CPC Class Codes: H01L 21/28026 characterised by the conductor H01L21/28176 takes precedence
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening.

Claims

1. A method of forming a semiconductor structure having a metal gate, the method comprising the following steps:

providing a semiconductor substrate;

forming at least a gate structure on the semiconductor substrate, the gate structure comprising a gate dielectric layer and a gate sacrificial layer;

forming a spacer structure on a peripheral side wall of the gate structure;

forming an interlayer dielectric layer covering the gate structure and the spacer structure;

planarizing the interlayer dielectric layer to expose the gate sacrificial layer;

removing a portion of the gate sacrificial layer to an initial etching depth to form an opening and expose a portion of the spacer structure;

removing a portion of the spacer structure exposed to the opening to broaden the opening;

removing the gate sacrificial layer completely; and

forming a gate conductive layer to fill the opening.

2. The method of claim 1, wherein the step of broadening the opening comprises an etching process.

3. The method of claim 1, wherein the step of broadening the opening comprises an ion bombardment process.

4. The method of claim 1, wherein the spacer structure comprises a first spacer and a second spacer, wherein the first spacer is disposed on the peripheral side wall of the gate structure and the second spacer is disposed on the peripheral side wall of the first spacer.

5. The method of claim 4, wherein the step of broadening the opening comprises partially removing the first spacer exposed to the opening till the initial etching depth.

6. The method of claim 4, wherein the first spacer comprises at least an oxide layer and at least a silicon nitride layer.

7. The method of claim 6, wherein the step of broadening the opening comprises removing the oxide layer and a part of the silicon nitride layer.

8. The method of claim 6, wherein a thickness of each of the oxide layers and the silicon nitride layers is substantially between 1 nm and 5 nm.

9. The method of claim 1, wherein the initial etching depth is at least larger than half of a height of the gate sacrificial layer in the step of removing the portion of the sacrificial layer to the initial etching step.

10. The method of claim 1, further comprising forming a work function layer before forming the conductive gate layer.

11. The method of claim 10, wherein the work function layer comprises an N-type work function metal material or a P type work function metal material.

12. The method of claim 11, wherein the N type work function metal material comprises titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), aluminum (Al), tantalum (Ta), titanium (Ti), titanium-aluminum (TiAl), titanium-aluminum-nitride (TiAlN) or hafnium (Hf).

13. The method of claim 11, wherein the P-type work function metal material comprises titanium nitride (TiN), tungsten (W), tungsten nitride (WN), platinum (Pt), nickel (Ni), ruthenium (Ru), tantalum carbonitride (TaCN) or oxidized tantalum carbonitride (TaCNO).

14. The method of claim 10, wherein the work function layer is a titanium nitride layer.

15. The method of claim 14, wherein a thickness of the titanium nitride layer is substantially between 5 nm and 15 nm.

16. A semiconductor structure having a metal gate, the semiconductor structure comprising at least:

a semiconductor substrate;

a gate structure disposed on the semiconductor substrate, the semiconductor structure comprising at least a gate dielectric layer and a gate conductive layer, wherein the gate conductive layer comprises a first metal portion and a second metal portion, and the second metal portion covers the first metal portion;

a first spacer disposed on the peripheral side wall of the first metal portion, and the second metal portion covering the top of the first spacer; and

a second spacer disposed on the peripheral side wall of the first spacer.

17. The structure of claim 16, wherein the first spacer comprises a plurality of substructure layers.

18. The structure of claim 17, wherein the thickness of each of the substructure layers is substantially between 1 nm and 5 nm.

19. The structure of claim 16, further comprising a work function layer disposed between the gate dielectric layer and the first metal portion.

20. The structure of claim 19, wherein the work function layer comprises an N type work function metal material or a P type work function metal material.

21. The structure of claim 20, wherein the N type work function metal material comprises titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), aluminum (Al), tantalum (Ta), titanium (Ti), titanium-aluminum (TiAl), titanium-aluminum-nitride (TiAlN) or hafnium (Hf).

22. The structure of claim 20, wherein the P type work function metal material comprises titanium nitride (TiN), tungsten (W), tungsten nitride (WN), platinum (Pt), nickel (Ni), ruthenium (Ru), tantalum carbonitride (TaCN) or oxidized tantalum carbonitride (TaCNO).

23. The structure of claim 19, wherein the work function layer is a titanium nitride layer.

24. The structure of claim 23, wherein a thickness of the titanium nitride layer is substantially between 5 nm and 15 nm.