MEMORY STRUCTURE HAVING VOLATILE AND NON-VOLATILE MEMORY PORTIONS
First Claim
1. A device, comprising:
- a fin field-effect transistor (finFET) comprising;
a first gate configured to switchably receive a first signal that is configured to turn on the finFET;
a second gate configured to switchably receive a second signal that is configured to turn on the finFET,wherein the first gate is coupled to a non-volatile memory.
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Accused Products
Abstract
A memory array is provided that includes a transistor having two active gates sharing a source, a drain, and a channel of the transistor. One of the active gates may be coupled to a volatile memory portion of a memory cell, such as a DRAM cell, and the other active gate may be coupled to a non-volatile memory portion, for example, a charge storage node such as a SONOS cell. Methods of operating the memory array are provided that include transferring data from the volatile memory portions to the non-volatile memory portions, transferring data from the non-volatile memory portions to the volatile memory portions, and erasing the non-volatile memory portions of a row of memory cells.
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Citations
24 Claims
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1. A device, comprising:
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a fin field-effect transistor (finFET) comprising; a first gate configured to switchably receive a first signal that is configured to turn on the finFET; a second gate configured to switchably receive a second signal that is configured to turn on the finFET, wherein the first gate is coupled to a non-volatile memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A device, comprising:
a fin field-effect transistor (finFET) comprising; a first gate coupled to a non-volatile memory portion; a second gate coupled to a volatile memory portion; and a fin disposed between the first gate and the second gate. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A device, comprising:
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a fin-shaped semiconductor; a first layer disposed on a side of the semiconductor, wherein the first layer comprises a first gate oxide; and a second layer disposed on a side of the semiconductor, wherein the second layer comprises a second gate oxide, a third gate oxide, and a charge storage layer disposed between the second gate oxide and the third gate oxide. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
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Specification