MEMORY STRUCTURE HAVING VOLATILE AND NON-VOLATILE MEMORY PORTIONS

• US 20110127596A1
• Filed: 02/11/2011
• Published: 06/02/2011
• Est. Priority Date: 03/20/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kirsch, Howard C., Ingalls, Charles, Juengling, Werner
• Granted Patent: US 8,149,619 B2
• Time in Patent Office: Days
• US Class Current: 257/298
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/36 the transistor being a FinFET
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A memory array is provided that includes a transistor having two active gates sharing a source, a drain, and a channel of the transistor. One of the active gates may be coupled to a volatile memory portion of a memory cell, such as a DRAM cell, and the other active gate may be coupled to a non-volatile memory portion, for example, a charge storage node such as a SONOS cell. Methods of operating the memory array are provided that include transferring data from the volatile memory portions to the non-volatile memory portions, transferring data from the non-volatile memory portions to the volatile memory portions, and erasing the non-volatile memory portions of a row of memory cells.

Claims

1. A device, comprising:

a fin field-effect transistor (finFET) comprising;

a first gate configured to switchably receive a first signal that is configured to turn on the finFET;

a second gate configured to switchably receive a second signal that is configured to turn on the finFET,

wherein the first gate is coupled to a non-volatile memory.

2. The device of claim 1, wherein the finFET comprises a fin disposed between the first gate and the second gate.

3. The device of claim 2, wherein the fin comprises a source, a drain, a channel, and a dielectric portion that extends through a width of the fin, the dielectric portion disposed between the source and the drain and adjacent to at least part of the channel.

4. The device of claim 1, wherein the finFET comprises a first layer comprising a gate oxide, a second layer, and a third layer comprising a gate oxide, wherein the first layer, second layer, and third layer are disposed adjacent to at least a portion of the channel and interposed between at least part of the source and at least part of the drain and interposed between at least part of the first gate.

5. The device of claim 4, wherein the second layer comprises silicon nitride, nanoparticles, or a combination thereof.

6. The device of claim 1, wherein the non-volatile memory comprises a charge storage node.

7. The device of claim 6, wherein the non-volatile memory comprises SONOS memory.

8. The device of claim 1, wherein the second gate is coupled to a volatile memory.

9. The device of claim 8, wherein the volatile memory comprises a capacitive element.

10. The device of claim 9, wherein the capacitive element is disposed on a drain of the finFET.

11. A device, comprising:

a fin field-effect transistor (finFET) comprising;

a first gate coupled to a non-volatile memory portion;

a second gate coupled to a volatile memory portion; and

a fin disposed between the first gate and the second gate.

12. The device of claim 11, wherein the fin comprises a source, a drain, a channel, and a dielectric portion that extends through a width of the fin, the dielectric portion disposed between the source and the drain and adjacent to at least part of the channel.

13. The device of claim 11, wherein the non-volatile memory comprises a charge storage node.

14. The device of claim 13, wherein the non-volatile memory comprises SONOS memory.

15. The device of claim 11, wherein the volatile memory comprises a capacitive element.

16. The device of claim 15, wherein the capacitive element is disposed on a drain of the finFET.

17. A device, comprising:

a fin-shaped semiconductor;

a first layer disposed on a side of the semiconductor, wherein the first layer comprises a first gate oxide; and

a second layer disposed on a side of the semiconductor, wherein the second layer comprises a second gate oxide, a third gate oxide, and a charge storage layer disposed between the second gate oxide and the third gate oxide.

18. The device of claim 17, comprising a first conductor disposed on the first layer.

19. The device of claim 18, comprising a second conductor disposed on the second layer.

20. The device of claim 17, wherein the fin-shaped semiconductor comprises a plurality of field effect transistors, where each field effect transistor comprises a source and a gate.

21. The device of claim 20, wherein the first layer is configured to allow operation of a plurality of volatile memory portions coupled to the plurality of field effect transistors.

22. The device of claim 21, wherein the plurality of volatile memory portions comprises a plurality of capacitive elements disposed on the drains of the plurality of field effect transistors.

23. The device of claim 20, wherein the source and drain of each of the plurality of field effect transistors are separated by a trench.

24. The device of claim 23, wherein the trench comprises a dielectric.