Multiple-Gate Semiconductor Device and Method

• US 20110127610A1
• Filed: 06/09/2010
• Published: 06/02/2011
• Est. Priority Date: 12/02/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Da-Wen, Weng, Li-Wen, Chan, Chien-Tai, Lin, Hsien-Chin, Lee, Tung Ying
• Granted Patent: US 8,426,923 B2
• Time in Patent Office: Days
• US Class Current: 257/365
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.

Claims

1. A semiconductor device comprising:

a substrate comprising a first fin and a second fin;

a first isolation region located between the first fin and the second fin;

a second isolation region located opposite the first fin from the first isolation region, the second isolation region extending into the substrate further than the first isolation region; and

a continuous source/drain region extending from the first fin to the second fin.

2. The semiconductor device of claim 1, further comprising a contact etch stop layer formed over the continuous source/drain region.

3. The semiconductor device of claim 1, wherein the continuous source/drain region at least partially extends over the second isolation region.

4. The semiconductor device of claim 1, further comprising:

a third fin in contact with the continuous source/drain region; and

a gate stack extending over the first fin, the second fin, and the third fin.

5. The semiconductor device of claim 4, further comprising a third isolation region located between the second fin and the third fin, the third isolation region extending into the substrate less than the second isolation region.

6. The semiconductor device of claim 1, wherein the first isolation region extends along a sidewall of the first fin no further than the continuous source/drain region.

7. The semiconductor device of claim 1, wherein the second isolation region has a first region and a second region, the second region having a height from the substrate that is larger than the first region.

8. A semiconductor device comprising:

a substrate comprising a plurality of fins;

a first multiple-gate transistor formed from a first one of the plurality of fins and a second multiple-gate transistor formed from a second one of the plurality of fins, wherein the first multiple-gate transistor and second multiple-gate transistor share a source/drain region;

a first isolation region located between the first multiple-gate transistor and the second multiple-gate transistor, the first isolation region extending into the substrate a first distance; and

a second isolation region located adjacent the first multiple-gate transistor and outside of a region between the first multiple-gate transistor and the second multiple-gate transistor, the second isolation region extending into the substrate a second distance greater than the first distance.

9. The semiconductor device of claim 8, wherein the first isolation region extends no further than the plurality of fins.

10. The semiconductor device of claim 9, further comprising a contact etch stop layer over the source/drain region.

11. The semiconductor device of claim 8, further comprising:

a third multiple-gate transistor formed from one of the plurality of fins; and

a third isolation region located in a region between the second multiple-gate transistor and the third multiple-gate transistor, the third isolation region extending into the substrate a third distance less than the second distance.

12. The semiconductor device of claim 8, wherein the second isolation region further comprises:

a first portion located beneath a gate electrode of the first multiple-gate transistor, the first portion having a top surface a first distance away from the substrate; and

a second portion located laterally separated from the gate electrode, the second portion having a top surface a second distance away from the substrate, the second distance being less than the first distance.

13. The semiconductor device of claim 12, wherein the first multiple-gate transistor further comprises:

a first spacer in contact with the top surface of the first portion of the second isolation region; and

a second spacer in contact with the top surface of the second portion of the second isolation region.

14. A method of forming a semiconductor device, the method comprising:

providing a substrate;

forming a plurality of fins in the substrate;

forming first isolation regions in the substrate, the first isolation regions extending a first depth from a surface of the substrate;

forming second isolation regions in the substrate, the second isolation regions extending a second depth from the surface of the substrate, the second depth being less than the first depth;

forming a gate dielectric, gate electrode, and spacers over a first portion of each of the semiconductor fins and the second isolation regions while leaving a second portion of each of the semiconductor fins and the second isolation regions exposed;

removing the second portion of each of the semiconductor fins and the second isolation regions; and

forming a source/drain region, the source/drain region connecting the plurality of semiconductor fins.

15. The method of claim 14, wherein the forming a source/drain region is done at least in part through an epitaxial growth process.

16. The method of claim 14, further comprising forming a contact etch stop layer over the source/drain region.

17. The method of claim 14, wherein the removing the second portion of each of the semiconductor fins and the second isolation regions further comprises recessing a portion of the first isolation regions.

18. The method of claim 17, further comprising forming second spacers in contact with the portion of the first isolation regions.

19. The method of claim 14, wherein the forming a source/drain region further comprises epitaxially growing the source/drain region to extend over the second isolation regions.

20. The method of claim 14, wherein the forming first isolation regions further comprises:

forming first trenches;

filling the first trenches with a dielectric material; and

recessing the dielectric material within the first trenches.