Semiconductor Package and Manufacturing Methods Thereof

• US 20110127654A1
• Filed: 11/29/2010
• Published: 06/02/2011
• Est. Priority Date: 11/27/2009
• Status: Abandoned Application

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Weng, Chaofu, Ou, Ying-Te, Hunt, John Richard, Fu, Chieh-Chen, Tsai, Li Chuan, Wu, Yi Ting
• Application Number:
  US12/955,782
• Publication Number:
  US 20110127654A1
• Time in Patent Office: Days
• US Class Current: 257/660
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/078 : Adhesive characteristics other than chemical
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15173 : in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/167 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor package and manufacturing methods thereof are provided. In one embodiment, the semiconductor package includes a die, a shield, a package body, and a redistribution layer. The die has an active surface and an inactive surface. The shield is disposed over the inactive surface of the die. The package body encapsulates the die and a first portion of the shield, where a first surface of the package body is substantially coplanar with the active surface of the die. The redistribution layer is disposed on the active surface of the die and on portions of the first surface of the package body.

Claims

1. A semiconductor package, comprising:

a die having an active surface and an inactive surface;

a shield disposed over the inactive surface of the die;

a package body encapsulating the die and a first portion of the shield wherein a first surface of the package body is substantially coplanar with the active surface of the die; and

a redistribution layer disposed on the active surface of the die and on portions of the first surface of the package body.

2. The semiconductor package of claim 1, wherein the shield includes a mesh portion that is encapsulated by the package body.

3. The semiconductor package of claim 2, wherein a pitch of the mesh portion is configured to protect against electromagnetic interference with specific parameters.

4. The semiconductor package of claim 1, wherein the redistribution layer includes a dielectric layer and a conductive layer having a first part and a second part, wherein the first part of the conductive layer is electrically connected to the active surface of the die.

5. The semiconductor package of claim 4, wherein the second part of the conductive layer includes a ground portion that extends through the dielectric layer and that electrically connects to the shield.

6. The semiconductor package of claim 1, wherein a second surface of the package body opposite to the first surface is substantially coplanar with a second portion of the shield.

7. The semiconductor package of claim 1, wherein the first surface of the package body is substantially coplanar with the first portion of the shield.

8. The semiconductor package of claim 1, wherein the shield has a side surface that is exposed on a lateral periphery of the semiconductor package.

9. A semiconductor package, comprising:

a die having an active surface;

a shield extending over the die, the shield comprising a lateral section and a central section;

a package body encapsulating the die but exposing the active surface, and encapsulating portions of the lateral section of the shield, the central section of the shield disposed on an exterior surface of the package body; and

a redistribution layer disposed on the active surface of the die and a first surface of the package body.

10. The semiconductor package of claim 9, wherein the lateral section of the shield is a contiguous element extending around a lateral periphery of the die.

11. The semiconductor package of claim 9, wherein the lateral section of the shield includes a plurality of discrete elements positioned around a lateral periphery of the die.

12. The semiconductor package of claim 9, wherein the central section of the shield is a conductive coating.

13. The semiconductor package of claim 9, wherein the central section of the shield is a conductive film attached to the lateral section by an adhesive layer.

14. The semiconductor package of claim 9, wherein the redistribution layer includes a dielectric layer and a conductive layer having a first part and a second part, wherein the first part of the conductive layer is electrically connected to the active surface of the die.

15. The semiconductor package of claim 14, wherein the second part of the conductive layer includes a ground portion that extends through the dielectric layer and that electrically connects to the shield.

16. The semiconductor package of claim 9, wherein the lateral section of the shield is exposed on an exterior surface of the semiconductor package.

17. The semiconductor package of claim 9, wherein the shield includes a mesh portion that is encapsulated by the package body.

18. A method of manufacturing a semiconductor package, comprising:

providing a die having an active surface;

placing a metal structure over the die, the metal structure including a mesh defining a plurality of openings;

encapsulating the metal structure and the die with an encapsulant such that the active surface of the die, portions of the metal structure, and portions of the encapsulant form a substantially coplanar surface, wherein the molding material traverses the plurality of openings to encapsulate the die; and

forming a redistribution layer on the substantially coplanar surfacc, the redistribution layer electrically connected to the active surface of the die.

19. The method of claim 18, wherein forming the redistribution layer includes forming a dielectric layer and forming a conductive layer having a first portion and a second portion, wherein the first portion of the conductive layer is electrically connected to the active surface of the die.

20. The method of claim 19, further comprising:

forming an aperture in the dielectric layer, the aperture exposing the metal structure;

wherein forming the second portion of the conductive layer includes forming a ground portion in the aperture that electrically connects to the metal structure.