POWER-ON RESET SIGNAL GENERATION CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS

• US 20110128053A1
• Filed: 12/31/2009
• Published: 06/02/2011
• Est. Priority Date: 11/30/2009
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: KWON, Jae Kwan, Chung, Sang Hwa
• Granted Patent: US 8,093,932 B2
• Time in Patent Office: Days
• US Class Current: 327/143
• CPC Class Codes: H03K 17/22 Modifications for ensuring a predetermined initial state when the supply voltage has been applied bi-stable generators H03K3/12

Abstract

A power-on reset signal generation circuit of a semiconductor memory apparatus includes an external voltage level detector configured to detect an external voltage and generate an external voltage detection signal; a band gap voltage generation unit configured to generate a band gap voltage in response to the external voltage detection signal; a level detection voltage dividing unit configured to divide the external voltage depending upon a level of the band gap voltage and generate a division voltage; and a power-on reset signal generation unit configured to compare the level of the band gap voltage with a level of the division voltage and generate a power-on reset signal.

Claims

1. A power-on reset signal generation circuit of a semiconductor memory apparatus, comprising:

an external voltage level detector configured to detect an external voltage and generate an external voltage detection signal;

a band gap voltage generation unit configured to generate a band gap voltage in response to the external voltage detection signal;

a level detection voltage dividing unit configured to divide the external voltage depending upon a level of the band gap voltage and generate a division voltage; and

a power-on reset signal generation unit configured to compare the level of the band gap voltage with a level of the division voltage and generate a power-on reset signal.

2. The power-on reset signal generation circuit according to claim 1, wherein the level detection voltage dividing unit comprises:

a band gap voltage level detector configured to detect the level of the band gap voltage and generate a band gap detection signal;

a voltage transfer switching section configured to output the external voltage as a transfer voltage in response to the band gap detection signal; and

a voltage dividing section configured to divide the transfer voltage and generate the division voltage.

3. The power-on reset signal generation circuit according to claim 2, wherein the band gap voltage level detector is configured to enable the band gap detection signal when the band gap voltage has a voltage level higher than a target level.

4. The power-on reset signal generation circuit according to claim 2, wherein the band gap voltage level detector comprises:

a voltage dropping part configured to drop the level of the band gap voltage and generate a drop voltage;

a level detecting part configured to be applied with the band gap voltage as a driving voltage and generate a drop detection signal in response to a level of the drop voltage; and

a driving part configured to drive the drop detection signal and output it as the band gap detection signal.

5. The power-on reset signal generation circuit according to claim 4, wherein the voltage dropping part substantially maintains a difference between the levels of the band gap voltage and the drop voltage.

6. The power-on reset signal generation circuit according to claim 4, wherein the level detecting part is configured to be applied with the band gap voltage as the driving voltage and enable the drop detection signal when the drop voltage is higher than a target level.

7. The power-on reset signal generation circuit according to claim 2, wherein the voltage transfer switching unit is configured to output the external voltage as the transfer voltage when the band gap detection signal is enabled, and suppress the external voltage from being outputted as the transfer voltage when the band gap detection signal is disabled.

8. The power-on reset signal generation circuit according to claim 1, wherein the power-on reset signal generation unit is configured to enable the power-on reset signal when the level of the band gap voltage is higher than the level of the division voltage, and disable the power-on reset signal when the level of the band gap voltage is lower than the level of the division voltage.

9. The power-on reset signal generation circuit according to claim 1, wherein the external voltage level detector is configured to enable the external voltage detection signal when a level of the external voltage is higher than a target level, and generate the band gap voltage when the external voltage detection signal is enabled.

10. A power-on reset signal generation circuit of a semiconductor memory apparatus, comprising:

a power-on reset signal generation unit configured to compare a band gap voltage with a division voltage and generate a power-on reset signal; and

a level detection voltage dividing unit configured to generate the division voltage by dividing an external voltage in response to a level of the band gap voltage.

11. The power-on reset signal generation circuit according to claim 10, wherein the level detection voltage dividing unit is configured to divide the external voltage and generate the division voltage when the level of the band gap voltage is higher than a target level.

12. The power-on reset signal generation circuit according to claim 11, wherein the level detection voltage dividing unit comprises:

a band gap voltage level detector configured to enable a band gap detection signal when the level of the band gap voltage is higher than the target level;

a voltage transfer switching section configured to output the external voltage as a transfer voltage when the band gap detection signal is enabled; and

a voltage dividing section configured to divide the transfer voltage and generate the division voltage.

13. The power-on reset signal generation circuit according to claim 10, wherein the power-on reset signal generation unit is configured to enable the power-on reset signal when the level of the band gap voltage is higher than a level of the division voltage, and disable the power-on reset signal when the level of the band gap voltage is lower than the level of the division voltage.

14. A power-on reset signal generation circuit of semiconductor memory apparatus, comprising:

a voltage dividing unit configured to divide an external voltage and generate a division voltage; and

a power-on reset signal generation unit configured to compare a level of a band gap voltage with a level of division voltage and generate a power-on reset signal when an enable signal is enabled and the level of the band gap voltage is higher than a target level.

15. The power-on reset signal generation circuit according to claim 14, wherein the power on reset signal generation unit comprises:

an activation control unit configured to connect a ground terminal to a sink node when the enable signal is enabled and the level of the band gap voltage is higher than the target level;

a first switching unit configured to connect the sink node to an output node when the ground terminal is connected to the sink node and the level of the band gap voltage is higher than the level of the division voltage; and

a second switching unit configured to connect the external voltage to the output node when the ground terminal is connected to the sink node and the level of the band gap voltage is higher than the level of the division voltage.

16. A power-on reset signal generation circuit of semiconductor memory apparatus, comprising:

a detection signal generation unit configured to generate a drop detection signal that transits to a level of a band gap voltage or a level of a ground voltage in response to the level of the band gap voltage;

a driving unit configured to drive a drop detection signal and generate a band gap detection signal that transits to a level of an external voltage or the level of the ground voltage;

a signal response type voltage dividing unit configured to divide the external voltage in response to the band gap detection signal and generate a division voltage; and

is a power-on reset signal generation unit configured to compare the level of the band gap voltage with a level of the division voltage and generate a power-on reset signal.

17. The power-on reset signal generation circuit according to claim 16, wherein the detection signal generation unit is configured to generate a drop voltage by dropping the level of the band gap voltage, transit the drop detection signal to the level of the ground voltage when a level of the drop voltage is higher than a target level, and transit the drop detection signal to the level of the band gap voltage when the level of the drop voltage is lower than the target level.

18. The power-on reset signal generation circuit according to claim 17, wherein the detection signal generation unit comprises:

a voltage dropping section configured to drop the band gap voltage and generate the drop voltage; and

a level detecting section configured to be applied with the band gap voltage and the ground voltage as driving voltages and generate the drop detection signal in response to the level of the drop voltage.

19. The power-on reset signal generation circuit according to claim 16, wherein the signal response type voltage dividing unit comprises:

a voltage transfer switching section configured to output the external voltage as a transfer voltage when the band gap detection signal is enabled and suppress the external voltage from being outputted as the transfer voltage when the band gap detection signal is disabled; and

a dividing section configured to divide the transfer voltage and generate the division voltage.

20. The power-on reset signal generation circuit according to claim 16, wherein the power-on reset signal generation unit is configured to enable the power-on reset signal when the level of the band gap voltage is higher than the level of the division voltage, and disable the power-on reset signal when the level of the band gap voltage is lower than the level of the division voltage.