METHODS AND APPARATUS FOR INDUCTORS WITH INTEGRATED PASSIVE AND ACTIVE ELEMENTS

• US 20110128084A1
• Filed: 12/01/2009
• Published: 06/02/2011
• Est. Priority Date: 12/01/2009
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Myers, Thomas, Bhagat, Maulin P., Jin, Jean, Klemens, Guy, Frederick, Norman L., Farazian, Mohammad, Deng, Junxiong, Hadjichristos, Aristotele, Lee, Ockgoo, Asuri, Bhushan S., Tasic, Aleksandar, Yan, Hongyan
• Granted Patent: US 8,633,777 B2
• Time in Patent Office: Days
• US Class Current: 331/167
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 27/40 Structural association with built-in electric component, e.g. fuse
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03F 1/523 for amplifiers using field-effect devices H03F1/526 takes precedence
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2203/45316 the AAC comprising one or more discrete inductive elements or coils
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/45188 Non-folded cascode stages

Abstract

An integrated circuit is described. The integrated circuit includes an inductor that has a large empty area in the center of the inductor. The integrated circuit also includes additional circuitry. The additional circuitry is located within the large empty area in the center of the inductor. The additional circuitry may include a capacitor bank, transistors, electrostatic discharge (ESD) protection circuitry and other miscellaneous passive or active circuits.

Claims

1. An integrated circuit comprising:

an inductor, wherein the inductor has an empty area in the center of the inductor; and

additional circuitry, wherein the additional circuitry is located within the empty area in the center of the inductor.

2. The integrated circuit of claim 1, wherein the additional circuitry comprises a capacitor bank.

3. The integrated circuit of claim 1, wherein the inductor is a tank inductor that is part of a voltage controlled oscillator (VCO).

4. The integrated circuit of claim 1, wherein the inductor is a tank inductor that is part of a low noise amplifier (LNA).

5. The integrated circuit of claim 4, wherein the additional circuitry comprises a tuning capacitor.

6. The integrated circuit of claim 4, wherein the additional circuitry comprises a supply voltage pad.

7. The integrated circuit of claim 1, wherein the inductor is a degeneration inductor that is part of a low noise amplifier (LNA).

8. The integrated circuit of claim 7, wherein the additional circuitry comprises a resistor capacitor (RC) clamp.

9. The integrated circuit of claim 7, wherein the additional circuitry comprises a ground pad.

10. The integrated circuit of claim 7, wherein the additional circuitry comprises an electrostatic discharge (ESD) pad.

11. The integrated circuit of claim 7, wherein the additional circuitry comprises electrostatic discharge (ESD) lines.

12. The integrated circuit of claim 1, wherein the inductor is a balun.

13. The integrated circuit of claim 12, wherein the additional circuitry comprises at least one of input tuning capacitors, output tuning capacitors, a ground pad, a supply pad, and electrostatic discharge (ESD) protection structures for the supply pad.

14. The integrated circuit of claim 1, wherein the additional circuitry comprises at least one of transistors, memory, switches, additional inductors, active circuit blocks, and passive circuit blocks.

15. The integrated circuit of claim 1, wherein the inductance and quality factor (Q) of the inductor are not negatively affected by the additional circuitry.

16. The integrated circuit of claim 1, wherein the inductor and the additional circuitry are located on the same layer of the integrated circuit.

17. A method for providing circuitry within an inductor, the method comprising:

providing an inductor on an integrated circuit;

providing additional circuitry within the inductor; and

optimizing interaction between the inductor and the circuitry.

18. The method of claim 17, wherein the additional circuitry comprises a capacitor bank.

19. The method of claim 17, wherein the inductor is a tank inductor that is part of a voltage controlled oscillator (VCO).

20. The method of claim 17, wherein the inductor is a tank inductor that is part of a low noise amplifier (LNA).

21. The method of claim 20, wherein the additional circuitry comprises a tuning capacitor.

22. The method of claim 20, wherein the additional circuitry comprises a supply voltage pad.

23. The method of claim 17, wherein the inductor is a degeneration inductor that is part of a low noise amplifier (LNA).

24. The method of claim 23, wherein the additional circuitry comprises a resistor capacitor (RC) clamp.

25. The method of claim 23, wherein the additional circuitry comprises a ground pad.

26. The method of claim 23, wherein the additional circuitry comprises an electrostatic discharge (ESD) pad.

27. The method of claim 23, wherein the additional circuitry comprises electrostatic discharge (ESD) lines.

28. The method of claim 17, wherein the inductor is a balun.

29. The method of claim 28, wherein the additional circuitry comprises at least one of input tuning capacitors, output tuning capacitors, a ground pad, a supply pad, and electrostatic discharge (ESD) protection structures for the supply pad.

30. The method of claim 17, wherein the additional circuitry comprises at least one of transistors, memory, switches, additional inductors, active circuit blocks, and passive circuit blocks.

31. The method of claim 17, wherein the inductance and quality factor (Q) of the inductor are not negatively affected by the additional circuitry.

32. The method of claim 17, wherein the inductor and the additional circuitry are located on the same layer of the integrated circuit.

33. An apparatus for providing circuitry within an inductor, comprising:

means for providing an inductor on an integrated circuit;

means for providing additional circuitry within the inductor; and

means for optimizing interaction between the inductor and the circuitry.

34. The apparatus of claim 33, wherein the additional circuitry comprises a capacitor bank.

35. The apparatus of claim 33, wherein the additional circuitry comprises at least one of input tuning capacitors, output tuning capacitors, a ground pad, a supply pad, and electrostatic discharge (ESD) protection structures for the supply pad.

36. The apparatus of claim 33, wherein the inductor comprises a tank inductor that is part of a voltage controlled oscillator (VCO).

37. An integrated circuit comprising:

an inductor; and

additional circuitry, wherein the additional circuitry is located underneath the inductor, and wherein the inductor is a choke inductor.

38. The integrated circuit of claim 37, wherein the choke inductor is part of a voltage controlled oscillator (VCO).

39. The integrated circuit of claim 37, wherein the additional circuitry comprises transistors or capacitors.

40. The integrated circuit of claim 37, wherein the additional circuitry comprises a mid voltage generator for voltage controlled oscillator (VCO) calibration.

41. The integrated circuit of claim 37, wherein the inductor has minimal capacitive coupling.

42. An integrated circuit comprising:

a voltage controlled oscillator (VCO) comprising;

a tank inductor;

a capacitor bank, wherein the capacitor bank is located inside of the tank inductor;

a choke inductor; and

a voltage generator, wherein the voltage generator is located underneath the choke inductor.

43. The integrated circuit of claim 42, wherein the capacitor bank comprises a control bus.

44. The integrated circuit of claim 43, wherein the control bus comprises serial bus interface (SBI) signals that are used to control the capacitance of the capacitor bank.

45. The integrated circuit of claim 42, wherein the tank inductor has a stretched coil design, wherein an inductor with a stretched coil design has a higher quality (Q) factor when circuitry is placed within the inductor.

46. The integrated circuit of claim 42, wherein the capacitor bank does not have a dense layout.

47. The integrated circuit of claim 42, wherein the tank inductor and the capacitor bank are separated by a large keep out.

48. The integrated circuit of claim 42, wherein the VCO is a receiving (RX) VCO.

49. The integrated circuit of claim 42, wherein the voltage generator is used for calibrating the VCO.