IMAGING APPARATUS

• US 20110128408A1
• Filed: 10/28/2010
• Published: 06/02/2011
• Est. Priority Date: 12/01/2009
• Status: Active Grant

• Current Assignee: Ricoh Company Limited
• Original Assignee: Ricoh Company Limited
• Inventors: Kasahara, Ryosuke, Ishigaki, Tomoko
• Granted Patent: US 8,624,999 B2
• Time in Patent Office: Days
• US Class Current: 348/231.2
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 7/0105 using a storage device with different write and read speed
• CPC Class Codes: H04N 7/012 Conversion between an interlaced and a progressive signal for graphics images G09G2310/0229
• CPC Class Codes: H04N 7/0127 by changing the field or frame frequency of the incoming video signal, e.g. frame rate converter

Abstract

An imaging apparatus, including an optical system forming an image of an optical image of an object; an imaging element imaging the optical image and producing image data at a frame frequency Ffs out of a frame frequency Ffr of NTSC system; a frame memory storing the image data; and a controller progressively writing the image data in the frame memory and interlacedly reading out the image data from the frame memory at the frame frequency Ffr of NTSC system. The frame memory is divided into at least three areas comprising a writing-in area and a read-out area, wherein the controller sequentially switches the areas of the frame memory and progressively writes one frame of image data in each area and interlacedly reads out one frame of image data from each area in sequence.

Claims

1. An imaging apparatus, comprising:

an optical system configured to form an optical image of an object;

an imaging element configured to image the optical image and produce image data at a frame frequency Ffs out of a frame frequency Ffr of NTSC system;

a frame memory configured to store the image data; and

a controller configured to progressively write the image data in the frame memory and interlacedly read out the image data from the frame memory at the frame frequency Ffr of NTSC system,

wherein the frame memory is divided into at least three areas each comprising a writing-in area and a read-out area, and

wherein the controller sequentially switches the areas of the frame memory and progressively writes one frame of image data in each area and interlacedly reads out one frame of image data from each area in sequence.

2. The imaging apparatus of claim 1, wherein the controller determines whether writing one frame of image data in an area the controller reads out next is completed when finishing reading out one frame of image data from an area, and reads out again one frame of image data from the area the controller has read out when not completed.

3. The imaging apparatus of claim 2, wherein the controller determines whether writing one frame of image data in an area after an area the controller reads out next is completed when finishing reading out one frame of image data from an area the controller reads out next and starts reading out image date from the area the controller reads out next when not completed, and skips the area the controller reads out next and starts reading out image date from the area after an area the controller reads out next when completed.

4. The imaging apparatus of claim 1, wherein the controller performs a predetermined image conversion process when reading out image data from the frame memory.

5. The imaging apparatus of claim 1, wherein the imaging element produces image data at a frame frequency Ffs having a constant frame cycle.

6. The imaging apparatus of claim 1, wherein the imaging element produces image data at a variable frame frequency Ffs having variable adjacent frame cycles and a frame cycle of NTSC system when averaged.

7. The imaging apparatus of claim 1, further comprising a single oscillator configured to generate a clock frequency for NTSC system,

wherein the controller controls the interlaced read-out from the frame memory at the frame frequency Ffr of NTSC system, based on a clock of the clock frequency for NTSC system from the oscillator, and

wherein the imaging element operates, receiving the clock of the clock frequency for NTSC system, and changes a blanking period in a vertical direction or a blanking period in a horizontal direction to produce image data at the frame frequency Ffs out of the frame frequency Ffr of NTSC system.

8. The imaging apparatus of claim 7, wherein the imaging element comprises a register configured to register a parameter value, and changes the blanking period in a vertical direction or the blanking period in a horizontal direction according to the parameter value.

9. The imaging apparatus of claim 8, further comprising a CPU configured to determine the parameter value of the register in the imaging element.

10. The imaging apparatus of claim 1, further comprising:

a single oscillator configured to generate a clock frequency for NTSC system,

wherein the controller controls the interlaced read-out from the frame memory at the frame frequency Ffr of NTSC system, based on a clock of the clock frequency for NTSC system from the oscillator, and

wherein the imaging element operates, receiving a clock out of the clock frequency for NTSC system.

11. The imaging apparatus of claim 10, wherein the imaging element converts the clock out of the clock frequency for NTSC system into a clock having a n-times frequency with a PLL and produces image data at the converted clock.

12. The imaging apparatus of claim 11, wherein the clock and the converted clock are not a common divisor or a common multiple of the clock frequency for NTSC system.

13. The imaging apparatus of claim 12, wherein the imaging element changes a blanking period in a vertical direction or a blanking period in a horizontal direction to produce image data at the frame frequency Ffs out of the frame frequency Ffr of NTSC system.

14. The imaging apparatus of claim 1, wherein the imaging element produces a frame synchronizing signal of the frame frequency Ffr together with image data, and

wherein the controller controls a read-out timing of the frame memory based on the frame synchronizing signal from the imaging element.