ESD PROTECTION APPARATUS AND ESD DEVICE THEREIN

• US 20110128658A1
• Filed: 11/30/2009
• Published: 06/02/2011
• Est. Priority Date: 11/30/2009
• Status: Active Grant

• Current Assignee: Nuvoton Technology Corporation (Winbond Electronics Corporation)
• Original Assignee: Nuvoton Technology Corporation (Winbond Electronics Corporation)
• Inventors: SU, Yu-Ti, HSU, Chung-Ti
• Granted Patent: US 8,405,941 B2
• Time in Patent Office: Days
• US Class Current: 361/57
• CPC Class Codes: H01L 27/0285 bias arrangements for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits H01L27/0281 takes precedence
• CPC Class Codes: H01L 29/7436 Lateral thyristors
• CPC Class Codes: H01L 29/749 with turn-on by field effect

Abstract

An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes a source region and a drain region. The source region is to be coupled to a low-level voltage. The drain region is disposed apart from the source region and includes a first P-type heavily doped region and at least one first N-type heavily doped region. The first P-type heavily doped region is configured to couple to a pad, and the first N-type heavily doped region is adjacent to the first P-type heavily doped region and floated. An electrostatic discharge protection apparatus is also disclosed herein.

Claims

1. An electrostatic discharge (ESD) protection device comprising:

a source region to be coupled to a low-level voltage; and

a drain region disposed apart from the source region, the drain region comprising a first P-type heavily doped region and at least one first N-type heavily doped region, the first P-type heavily doped region being configured to couple to a pad, the first N-type heavily doped region being adjacent to the first P-type heavily doped region and floated.

2. The ESD protection device as claimed in claim 1, further comprising:

an N-type buffer region, the first P-type heavily doped region and the first N-type heavily doped region being formed in the N-type buffer region.

3. The ESD protection device as claimed in claim 2, further comprising:

is a P-type body region; and

an N-type well region, the P-type body region and the N-type buffer region being formed in the N-type well region.

4. The ESD protection device as claimed in claim 3, further comprising:

a P-type contact region disposed in the P-type body region and configured to couple to the low-level voltage such that the P-type body region couples to the low-level voltage through the P-type contact region.

5. The ESD protection device as claimed in claim 2, further comprising:

a P-type well region, the N-type buffer region and the source region being formed in the P-type well region.

6. The ESD protection device as claimed in claim 1, wherein the source region further comprises a second N-type heavily doped region to be coupled to the low-level voltage.

7. An electrostatic discharge (ESD) protection apparatus comprising:

a phase shift circuit having a transient response and generating a icy response voltage according to the transient response when receiving electrostatic discharge charges;

a transistor switch circuit triggered by the response voltage to turn on and generate a control voltage based on the electrostatic discharge charges; and

a first metal-oxide-semiconductor field effect transistor (MOSFET) turning on according to the control voltage and having a parasitical silicon controlled rectifier (SCR) equivalent circuit, wherein the electrostatic discharge charges are discharged through the SCR equivalent circuit when the first MOSFET is turned on by the control voltage, and the first MOSFET further comprises;

a P-type heavily doped region configured to couple to a pad and to be an anode of the SCR equivalent circuit; and

at least one N-type heavily doped region being adjacent to the P-type heavily doped region and floated.

8. The ESD protection apparatus as claimed in claim 7, wherein the phase shift circuit further comprises:

an equivalent resistor having one terminal for receiving the electrostatic discharge charges; and

an equivalent capacitor connected with the equivalent resistor in series, wherein the response voltage is generated at the connection of the equivalent capacitor with the equivalent resistor.

9. The ESD protection apparatus as claimed in claim 8, wherein the equivalent capacitor is a second MOSFET, and the second MOSFET has a gate and a source both coupled to a low-level voltage and has a drain connected with the equivalent resistor.

10. The ESD protection apparatus as claimed in claim 8, wherein the equivalent capacitor is a second MOSFET, and the second MOSFET has a gate connected with the equivalent resistor and has a drain and a source both coupled to a low-level voltage.

11. The ESD protection apparatus as claimed in claim 7, wherein the transistor switch circuit further comprises:

a transistor switch for receiving the response voltage and triggered by the response voltage to turn on; and

an equivalent resistor coupled to the transistor switch and generating the control voltage at a coupling node between the equivalent resistor and the transistor switch based on the electrostatic discharge charges when the transistor switch turns on.

12. The ESD protection apparatus as claimed in claim 11, wherein the transistor switch is a P-type transistor having a gate for receiving the response voltage, a source for receiving the electrostatic discharge charges, and a drain coupled to the equivalent resistor.

13. An electrostatic discharge (ESD) protection apparatus comprising:

a first metal-oxide-semiconductor field effect transistor (MOSFET) coupled between a pad and a low-level voltage, the first MOSFET having a parasitical silicon controlled rectifier (SCR) equivalent circuit and comprising;

a P-type heavily doped region, the first MOSFET being coupled through the P-type heavily doped region to the pad, the P-type heavily doped region being an anode of the SCR equivalent circuit; and

at least one N-type heavily doped region being adjacent to the P-type heavily doped region and floated;

a first equivalent resistor coupled between a gate of the first MOSFET and the low-level voltage;

a transistor switch coupled between the pad and the first equivalent resistor and configured to conduct currents between the pad and the first equivalent resistor;

a second equivalent resistor coupled between the pad and a control terminal of the transistor switch; and

an equivalent capacitor coupled between the control terminal of the transistor switch and the low-level voltage;

wherein when electrostatic discharge charges occurs on the pad, the transistor switch conducts currents between the pad and the first equivalent resistor, such that the first MOSFET turns on and the electrostatic discharge charges are discharged through the SCR equivalent circuit.

14. The ESD protection apparatus as claimed in claim 13, wherein the first equivalent resistor is a transistor.

15. The ESD protection apparatus as claimed in claim 13, wherein the transistor switch is a P-type transistor, a source of the P-type transistor being coupled to the pad, a drain of the P-type transistor being coupled to the first equivalent resistor and a gate of the first MOSFET.

16. The ESD protection apparatus as claimed in claim 15, wherein the equivalent capacitor is a second MOSFET, a gate and a source of the second MOSFET being coupled to the low-level voltage, a drain of the second MOSFET being coupled to a gate of the P-type transistor.

17. The ESD protection apparatus as claimed in claim 13, wherein the equivalent capacitor is a second MOSFET, a drain and a source of the second MOSFET being coupled to the low-level voltage, a gate of the second MOSFET being coupled to a gate of the P-type transistor.

18. The ESD protection apparatus as claimed in claim 13, wherein when the electrostatic discharge charges occurs on the pad, the second equivalent resistor operates with the equivalent capacitor in accordance with a transient response to turn on the first MOSFET.

19. The ESD protection apparatus as claimed in claim 13, wherein the first MOSFET is a lateral diffusion MOSFET or a high voltage MOSFET.