PREAMBLE DETECTION AND POSTAMBLE CLOSURE FOR A MEMORY INTERFACE CONTROLLER

• US 20110128793A1
• Filed: 02/10/2011
• Published: 06/02/2011
• Est. Priority Date: 06/10/2009
• Status: Active Grant

• Current Assignee: Juniper Networks Incorporated
• Original Assignee: Juniper Networks Incorporated
• Inventors: VENKATARAMAN, Srinivas, GARAPALLY, Praveen
• Granted Patent: US 8,023,342 B2
• Time in Patent Office: Days
• US Class Current: 365/189.02
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory controller, such as a memory controller for reading data received from a DDR SDRAM memory, may detect the beginning and end of a read cycle. The memory controller may include a preamble detection circuit to receive a strobe signal and output a first control signal indicating detection of a preamble window in the strobe signal that indicates a beginning of the read cycle, where the first control signal is delayed based on a selectable delay period applied to the first control signal. The memory controller may further include a first gate to, based on the first control signal, either output the strobe signal for reading of the data lines or block the strobe signal, and the control logic to set an amount of the selectable delay period for the preamble detection circuit.

Claims

1-23. -23. (canceled)

24. A device comprising:

a memory; and

a memory controller comprising;

a preamble detection circuit comprising;

a first multiplexer, and

a second multiplexer to provide a first signal indicating detection of a beginning of a read cycle from the memory;

control logic to select outputs of the first multiplexer and the second multiplexer,

where the control logic is to determine the outputs to select for the first multiplexer and the second multiplexer during a training cycle in which a strobe signal is sampled over a plurality of data read cycles, and in which, during different ones of the plurality of data read cycles, different combinations of the outputs of the first multiplexer and the second multiplexer are selected, and

where the control logic is to perform the training cycle when the device is initially powered-up or reset; and

a first gate connected to output the strobe signal or block the strobe signal based on the first signal.

25. The device of claim 24,

where the preamble detection circuit further comprises a plurality of flip-flops connected to sample the strobe signal on rising and falling edges of a clock cycle, and

where the first multiplexer is connected to outputs of the plurality of flip-flops and is to select one of the outputs of the plurality of flip-flops to output from the first multiplexer.

26. The device of claim 24,

where the preamble detection circuit further comprises a plurality of serially connected delay elements connected, at a first of the plurality of serially connected delay elements, to receive an output of the first multiplexer, and

where the second multiplexer is connected to select an output corresponding to one of the plurality of serially connected delay elements and to provide the output as the first signal.

27. The device of claim 24, where the memory controller is to control reading from the memory by reading data from a plurality of data lines, in which the data is read by sampling the data on rising and falling edges of the strobe signal received from the memory.

28. The device of claim 24, where the memory controller further comprises:

a second gate connected to receive the first signal and a second signal and to output a signal to the first gate in response thereto.

29. The device of claim 28, where the second gate is a logical OR gate and the first gate is a logical NAND gate.

30. The device of claim 24,

where the memory controller further comprises a postamble detection circuit to output a second signal,

where the first gate outputs the strobe signal or blocks the strobe signal further based on the second signal, and

where the second signal indicates an end of the read cycle from the memory.

31. The device of claim 30, where the control logic performs the training cycle when the memory controller is initially powered-up or reset.

32. A memory controller comprising:

a preamble detection circuit comprising;

a first multiplexer, and

a second multiplexer to provide a first signal indicating detection of a beginning of a read cycle from a memory device;

a postamble detection circuit to output a second signal indicating an end of the read cycle from the memory device;

a first gate connected to output a strobe signal or block the strobe signal based on the first signal and the second signal; and

control logic to output signals that control a selection of the first multiplexer and the second multiplexer,

where the control logic is to determine the selection of the first multiplexer and the second multiplexer during a training cycle in which the strobe signal is sampled over a plurality of data read cycles, and in which, during different ones of the plurality of data read cycles, different combinations of outputs of the first multiplexer and the second multiplexers are selected.

33. The memory controller of claim 32, further comprising:

a plurality of flip-flops connected to sample the strobe signal on rising and falling edges of a clock cycle, and

a plurality of serially connected delay elements connected, at a first of the plurality of serially connected delay elements, to receive an output of the first multiplexer.

34. The memory controller of claim 33, where the first multiplexer is connected to outputs of the plurality of flip-flops and is to select one of the outputs of the plurality of flip-flops as an output from the first multiplexer.

35. The memory controller of claim 33, where the second multiplexer is connected to select an output corresponding to one of the plurality of serially connected delay elements and to provide the output as the first signal.

36. The memory controller of claim 32, further comprising:

a second gate connected to receive the first signal and the second signal and to output a signal to the first gate in response thereto.

37. The memory controller of claim 36, where the second gate is a logical OR gate and the first gate is a logical NAND gate.

38. A method comprising:

determining a delay during a training cycle in which a strobe signal is sampled over a plurality of data read cycles, and in which, during different ones of the plurality of data read cycles, different combinations of outputs of a first multiplexer and a second multiplexer are selected;

selecting a first output corresponding to one of a plurality of flip-flops, to output from the first multiplexer, based on the delay;

providing to the first output to a plurality of serially connected delay elements;

selecting a second output corresponding to one of the plurality of serially connected delay elements, to output as a first signal from the second multiplexer, based on the delay; and

controlling a gate to pass or block the strobe signal based on the first signal.

39. The method of claim 38, further comprising:

reading data from a plurality of data lines, in which the data is read by sampling the data on rising and falling edges of the strobe signal received from memory.

40. The method of claim 38, further comprising:

outputting a second signal indicating an end of a read cycle from memory.

41. The method of claim 40, further comprising:

controlling the gate to output the strobe signal or block the strobe signal based on the second signal.

42. The method of claim 38, where the first signal indicates detection of a beginning of a read cycle from a memory.

43. The method of claim 42, where determining the delay comprises optimizing the read cycle.