SYNCHRONIZED SYSTEM FOR DISTRIBUTING AND PROCESSING SIGNALS, IN PARTICULAR AUDIO SIGNALS IN A WIRELESS LOUDSPEAKER NETWORK

• US 20110129048A1
• Filed: 08/26/2008
• Published: 06/02/2011
• Est. Priority Date: 09/06/2007
• Status: Abandoned Application

• Current Assignee: Parrot SA
• Original Assignee: Parrot SA
• Inventors: Pignal, Pierre, Barbe, Christophe, Lemoine, Yves
• Application Number:
  US12/675,931
• Publication Number:
  US 20110129048A1
• Time in Patent Office: Days
• US Class Current: 375/371
• CPC Class Codes: H04J 3/0658 Clock or time synchronisation among packet nodes
• CPC Class Codes: H04W 56/0015 one node acting as a reference for the others

Abstract

The system comprises a master device (10) and at least one slave device (20). Each device has wireless transceiver and interface means (12, 22), a digital signal processor (14, 24), and a clock (16, 26). The master device transmits signals at a rate defined by its clock (16). The slave device has means for determining the frequency offset between the clocks and for correcting accordingly the rate at which signals are delivered internally to its processor. At the slave end, the frequency of the external clock(s) (26) is controllable about its nominal value, and means are provided for extracting a frequency offset value from a register (50) and for responding thereto by adjusting the frequency of the second clock in the direction tending to minimize the offset. The processor (24) of the slave device is thus enabled to operate synchronously with the clocking of signals delivered over the wireless connection, as played back by the interface circuit after the clock rate of the signals has been corrected internally.

Claims

1. A signal distribution system, in particular for radio signals in a wireless loudspeaker network, the system comprising at least two devices (10, 20) that are continuously coupled together by a wireless connection (32), and comprising:

a master device (10) comprising;

first transmission and interface means (12);

a first digital signal processor (14); and

a first clock (16) for common clocking of the first transmission and interface means and of the first digital signal processor;

 

the master device transmitting signals via said wireless connection (32) at a rate that is defined by said first clock (16);

at least one slave device (20) comprising;

second transmission and interface means (22);

a second digital signal processor (24); and

a second clock (26) for common clocking of the second transmission and interface means and of the second digital signal processor;

 

the second transmission and interface means (22) including internal resynchronization means, having internal correlator and compensator means for determining a frequency offset between firstly the clock rate of the signals received by the second transmission and interface means, and secondly the frequency of the second clock, and for correcting the rate at which signals are delivered to the second digital signal processor by the second transmission and interface means as a function of the frequency offset as determined in this way;

the system being characterized in that the second clock (26) is a clock that is external relative to said second transmission and interface means, and presents a frequency that is controllable about its nominal value; and

in that the slave device further comprises;

interrogator means for extracting the value of said frequency offset from the correlator and compensator means; and

servo-control means (54, 56, 58) for applying said offset as extracted in this way to the second clock so as to control the frequency of the second clock in response to said frequency offset value, in the direction tending to minimize said offset.

2. The system of claim 1, wherein the interrogator means are means (52) for reading the content of an internal register (50) of the correlator and compensator means.

3. The system of claim 1, wherein the interrogator means are incorporated in the second digital processor (24).

4. The system of claim 1, wherein the second digital signal processor (24) includes means for delivering a signal (54) for controlling the frequency of the second clock.

5. The system of claim 4, wherein the control signal (54) is a digital signal.

6. The system of claim 5, wherein the control signal (54) is a pulse width modulated (PWM) signal.

7. The system of claim 6, wherein the control signal (54) is delivered to the second clock (26) via a lowpass filter (56).

8. The system of claim 1, wherein the accuracy of the first and second clocks (16, 26) is at best 10 ppm, and preferably at best 20 ppm.