SYSTEMS AND METHODS FOR LOW WEAR OPERATION OF SOLID STATE MEMORY

• US 20110131444A1
• Filed: 12/02/2009
• Published: 06/02/2011
• Est. Priority Date: 12/02/2009
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Ulriksson, Bengt A., Buch, Bruce D., Patapoutian, Ara, Rub, Bernardo
• Granted Patent: US 8,130,553 B2
• Time in Patent Office: Days
• US Class Current: 714/6.1
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

This disclosure is related to systems and methods for low wear operation of solid state memory, such as a flash memory. In one example, a controller is coupled to a memory and adapted to dynamically adjust programming thresholds over the course of usage of the data storage device such that a signal-to-noise ratio from reading data stored in the data storage cells is no less than a minimum amount needed to recover the data using an enhanced error detection capability.

Claims

1. A memory device comprising:

an array of data storage cells;

a control circuit connected to the array of data storage cells, wherein the data storage cells can be electrically programmed and erased by applying a first programming voltage and programming pulse sequence to achieve a first charge transfer and a first threshold voltage having a first signal-to-noise ratio, the control circuit adapted to;

program the data storage cells by applying a second programming voltage and programming pulse sequence to achieve a second charge transfer that is less than the first charge transfer and a second threshold voltage that is less than the first threshold voltage, the second threshold voltage providing a second signal-to-noise ratio that is lower than the first signal-to-noise ratio.

2. The device of claim 1, wherein the control circuit is adapted to apply the second programming voltage and programming pulse sequence during continuous, normal operation of the memory device.

3. The device of claim 1, further comprising a memory coupled to the control circuit, the memory comprising a register to store an indicator of an amount of voltage to apply to the data storage cells, and the control circuit configured to check the value stored in the register to determine when to implement the second programming voltage.

4. The device of claim 3, wherein the memory further comprises a second register to store a value indicative of a programming current pulse width and a third register to store a value indicative of an erase current time.

5. The device of claim 1, wherein the memory further comprises a fourth register to store a value indicative of a number of programming current pulses to be applied and the control circuit configured to reduce the number of programming current pulses applied for the second voltage compared to a number of programming current pulses applied during the first current.

6. The device of claim 1, further comprising a first detection capability to recover data from a data storage cell containing a first voltage that is greater than the first threshold voltage and a second detection capability to recover data from a data storage cell containing a second voltage that is less than the first threshold voltage.

7. The device of claim 6, wherein the second voltage is below a voltage amount for what is required for feasible read recovery without using the second detection capability.

8. The device of claim 7, wherein the control circuit is adapted to:

determine a minimum signal-to-noise ratio needed to read data while using the second detection capability;

set the second voltage based on the minimum signal-to-noise ratio;

monitor a signal-to-noise ratio of the data storage cells with relation to program and erase cycles; and

adjust the second voltage when the signal-to-noise ratio is lower than the minimum signal-to-noise ratio.

9. The device of claim 8, wherein the second voltage is continually monitored and adjusted to keep the signal-to-noise ratio within a specified range above the minimum signal-to-noise ratio.

10. A method comprising:

providing a memory having data storage cells, wherein the data storage cells can be electrically programmed and erased by applying a programming voltage and programming sequence to induce a charge transfer that changes a first threshold voltage, wherein when programmed and subsequently read, the data storage cells with the first threshold voltage programmed produce a first signal-to-noise ratio;

programming and erasing the data storage cells by applying a second programming voltage and programming sequence to achieve a second threshold voltage that is less than the first threshold voltage, which produces a second signal-to-noise ratio that is lower than the first signal-to-noise ratio; and

retrieving data stored in the data storage cells using a second detection capability that is greater than a first detection capability, the second detection capability adapted to recover data stored using the second threshold voltage, wherein the first detection capability is not capable of recovering data stored using the second threshold voltage.

11. The method of claim 10, wherein the second threshold voltage is an amount below what is required for feasible read recovery without using the second detection capability.

12. The method of claim 11, further comprising applying the second programming voltage and programming sequence during continuous, normal operation of the memory.

13. The method of claim 12, further comprising:

determining a minimum signal-to-noise ratio needed to read data while using the first detection capability;

setting the second threshold voltage based on the minimum signal-to-noise ratio;

monitoring the second threshold voltage; and

adjusting the second threshold voltage to keep the signal-to-noise ratio within a specified range above the minimum signal-to-noise ratio.

14. The method of claim 13, further comprising determining signal-to-noise ratio based on a number of errors per read.

15. A data storage device comprising:

a memory having a control circuit and electrically programmable and erasable data storage cells having programming thresholds for programming the data storage cells; and

a controller coupled to the memory and adapted to dynamically adjust the programming thresholds over the course of usage of the data storage device such that a signal-to-noise ratio from reading data stored in the data storage cells is no less than a minimum amount needed to recover the data using an error detection capability.

16. The data storage device of claim 15, further comprising:

the data storage cells adapted to be programmed and erased by applying a first programming voltage and pulse sequence to achieve a threshold voltage;

the controller adapted to;

program and erase the data storage cells by applying a second programming voltage and pulse sequence to achieve a second threshold voltage that is less than the first threshold voltage, the second threshold voltage providing a signal-to-noise ratio that is lower than a first signal-to-noise ratio that would be caused by applying the first threshold voltage; and

retrieve the data stored in the data storage cells using the error detection capability.

17. The data storage device of claim 16, wherein the second threshold voltage is an amount below what is required for feasible read recovery without using the error detection capability.

18. The data storage device of claim 17, further comprising a first detection capability to recover data from a data storage cell programmed with a threshold voltage greater than the second threshold voltage and a second detection capability to recover data from a data storage cell containing a voltage less than the first threshold voltage.

19. The data storage device of claim 16, wherein the controller is adapted to:

determine a minimum signal-to-noise ratio needed to read data while using the enhanced detection capability;

set the second threshold voltage based on the minimum signal-to-noise ratio;

monitor a signal-to-noise ratio of the data storage cells with relation to program and erase cycles; and

adjust the second threshold voltage based on the signal-to-noise ratio and the minimum signal-to-noise ratio.

20. The data storage device of claim 19, wherein the second threshold voltage is continually monitored and adjusted to keep the signal-to-noise ratio within a specified range above the minimum signal-to-noise ratio.

21. The data storage device of claim 20, wherein the signal-to-noise ratio is determined by monitoring a distribution of errors when reading data from the data storage cells and the minimum signal-to-noise ratio represents a maximum amount of errors that can be corrected per read.

22. The data storage device of claim 15, wherein the memory comprises multi-level cell (MLC) NAND non-volatile memory.