Apparatus and Method of PAGE Program Operation for Memory Devices with Mirror Back-Up of Data

• US 20110131445A1
• Filed: 02/07/2011
• Published: 06/02/2011
• Est. Priority Date: 02/22/2007
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: OH, HakJune, PYEON, Hong Beom, KIM, Jin-Ki
• Granted Patent: US 8,060,691 B2
• Time in Patent Office: Days
• US Class Current: 714/6.2
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 13/4247 on a daisy chain bus

Abstract

An apparatus and method of page program operation is provided. When performing a page program operation with a selected memory device, a memory controller loads the data into the page buffer of one selected memory device and also into the page buffer of another selected memory device in order to store a back-up copy of the data. In the event that the data is not successfully programmed into the memory cells of the one selected memory device, then the memory controller recovers the data from the page buffer of the other memory device. Since a copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in its data storage elements.

Claims

1. A method for communicating with a serial interconnection of a plurality of memory devices interconnected in-series, the serial interconnection including at least first and second memory devices, each of the first and second memory devices having a store element and memory cells and being associated with a unique address in the serial interconnection, the method comprising:

loading data stored in a data storage to the store elements of the first and second memory devices of the serial interconnection;

instructing the first memory device to program the data loaded in its store element into its memory cells;

determining whether the data is successfully programmed into the memory cells of the first memory device, if not successfully programmed, a failure determination being provided; and

recovering the data from the store element of the second memory device in response to the failure determination.

2. The method of claim 1, wherein the step of recovering comprises:

reading back the data from the store element of the second memory device without programming the loaded data into the memory cells of the second memory device.

3. The method of claim 2, further comprising:

loading the recovered data to the store elements of the first and second memory devices of the serial interconnection; and

programming the loaded data into the memory cells of the first memory device.

4. The method of claim 2, further comprising:

freeing up space in the data storage where the data is stored before recovering the data loaded in the store element of the second memory device.

5. The method of claim 4, further comprising:

storing the recovered data in the data storage.

6. The method of claim 5, further comprising:

loading the data in the data storage to the store elements of the first and second memory devices of the serial interconnection; and

programming the loaded data into the memory cells of the first memory device.

7. The method of claim 1, wherein the step of loading comprises:

transmitting a command to the serial interconnection, the command including address information for addressing a device of the serial interconnection.

8. The method of claim 7, wherein the address information is addressing the first and second memory devices of the serial interconnection.

9. The method of claim 8, wherein,

at each of the first and second memory devices, determining whether the command is addressed based on the address information and the unique address associated with the first memory device, in a case of the first and second memory devices being addressed, an address determination being provided.

10. The method of claim 9, wherein the step of loading further comprises:

loading the data to the store elements of the first and second memory devices, in response to the address determination.

11. The method of claim 9, wherein the address information includes:

a first address for addressing the first memory device; and

a second address for addressing the second memory device.

12. The method of claim 9, wherein the address information includes single address information represented by a plurality of binary bits, the binary bits without one bit corresponding to the unique addresses associated with the first and second memory devices.

13. The method of claim 12, wherein:

the single address information is represented by a plurality of binary bits,

each of the unique addresses of the first and second memory devices is represented by a plurality of binary bits.

14. The method of claim 13, wherein:

at each of the first and second memory devices, determining whether the plurality of binary bits of the single address information excluding the least significant bit matches each of the unique addresses of the first and second memory devices excluding the least significant bit.