SOLAR CELL AND METHOD OF MANUFACTURING THE SAME

• US 20110132441A1
• Filed: 06/29/2009
• Published: 06/09/2011
• Est. Priority Date: 06/30/2008
• Status: Abandoned Application

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Asaumi, Toshio, Sakata, Hitoshi
• Application Number:
  US13/001,732
• Publication Number:
  US 20110132441A1
• Time in Patent Office: Days
• US Class Current: 136/252
• CPC Class Codes: H01L 31/022441 Electrode arrangements specially adapted for back-contact solar cells
• CPC Class Codes: H01L 31/03529 Shape of the potential jump barrier or surface barrier
• CPC Class Codes: H01L 31/0682 back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
• CPC Class Codes: H01L 31/0747 comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
• CPC Class Codes: H01L 31/075 the potential barriers being only of the PIN type, e.g. amorphous silicon PIN solar cells
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells
• CPC Class Codes: Y02E 10/548 Amorphous silicon PV cells

Abstract

In a solar cell comprising a semiconductor substrate 11 and a i-type amorphous semiconductor layer 12 formed on a back surface of the semiconductor substrate 11, the i-type amorphous semiconductor layer 12 includes an exposed portion 12A exposed in a planer view, and a covered portion 12B covered with each of the p-type semiconductor layer 13 and the n-type semiconductor layer 14. A thickness T₁ of the exposed portion 12A is less than a thickness T₂ of the covered portion 12B.

Claims

1. A solar cell comprising:

a semiconductor substrate having a light receiving surface and a back surface provided on an opposite side of the light receiving surface;

a amorphous semiconductor layer, substantially intrinsic, and formed on the back surface;

a p-type semiconductor layer formed on the amorphous semiconductor layer; and

an n-type semiconductor layer formed on the amorphous semiconductor layer, wherein

the amorphous semiconductor layer includes an exposed portion exposed in a planer view from the back surface side, and a covered portion covered with each of the p-type semiconductor layer and the n-type semiconductor layer in the planer view, and

a first thickness being a thickness of the exposed portion is less than a second thickness being a thickness of the covered portion.

2. The solar cell according to claim 1, wherein

a ratio of the first thickness relative to the second thickness is 0.48 or more but less than 1.

3. The solar cell according to claim 1, wherein

the first thickness is 1.44 nm or more but less than 25 nm.

4. A method of manufacturing a solar cell which includes a semiconductor substrate having a light receiving surface and a back surface provided on an opposite side of the light receiving surface, the method comprising the steps of:

forming a first amorphous semiconductor layer substantially intrinsic on the back surface;

forming a second amorphous semiconductor substantially intrinsic on a first region and on a second region provided in a surface of the first amorphous semiconductor layer;

forming a p-type semiconductor layer on the second amorphous semiconductor layer formed on the first region; and

forming an n-type semiconductor layer on the second amorphous semiconductor layer formed on the second region.