High-Speed Ceramic Modules with Hybrid Referencing Scheme for Improved Performance and Reduced Cost

• US 20110132650A1
• Filed: 12/04/2009
• Published: 06/09/2011
• Est. Priority Date: 12/04/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Becker, Wiren D., Zhou, Tingdong, Choi, Jinwoo
• Granted Patent: US 8,339,803 B2
• Time in Patent Office: Days
• US Class Current: 174/261
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/19051 Impedance matching structure [e.g. balun]
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/0253 Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings H05K1/0251 takes precedence
• CPC Class Codes: H05K 2201/09309 Core having two or more power planes; Capacitive laminate of two power planes
• CPC Class Codes: H05K 2201/09681 Mesh conductors, e.g. as a ground plane
• CPC Class Codes: H05K 2201/09727 Varying width along a single conductor; Conductors or pads having different widths
• CPC Class Codes: H05K 2201/10674 Flip chip
• CPC Class Codes: H05K 3/4629 laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base

Abstract

A multi-layered ceramic package comprises: a signal layer with identified chip/device area(s)/site(s) that require a supply of power; and a voltage power (Vdd) layer and a ground (Gnd) layer disposed on opposite sides directly above or below (adjacent to) the signal layer and providing a first reference mesh plane and a second reference mesh plane configured utilizing a hybrid mesh scheme. The hybrid mesh scheme comprises different mesh configurations from among: a full dense mesh in a first area directly above or below the identified chip/device area(s); a half dense mesh in a second area that is above or below the edge(s) of the chip/device area; and a wider mesh pitch in all other areas, and the Vdd traces are aligned to run parallel and adjacent to signal lines in those other areas. Wider traces are provided within the mesh areas that run parallel and adjacent to signal lines.

Claims

1. A multi-layered ceramic package comprising:

a signal layer having one or more high power usage (HPU) area and one or more second areas that are not HPU areas, wherein the HPU areas provide a supply of power for operation of one or more devices located within the HPU areas;

a reference mesh layer disposed on a first side directly above or below the signal layer and providing a first reference mesh plane that is configured according to a hybrid mesh scheme;

wherein the hybrid mesh scheme comprises two or more mesh densities within the single reference mesh layer from among;

a full dense mesh in a first area of the reference mesh layer that is directly adjacent to the one or more HPU area in the signal layer;

a half dense mesh in a second area of the reference mesh layer that is adjacent to one or more perimeter edges of and proximate to the HPU area in the signal layer; and

a low density mesh in all other areas of the reference mesh layer that are not adjacent or proximate to the HPU area within the signal layer.

2. The multi-layered ceramic package of claim 1, wherein the reference mesh layer is one of a voltage power (Vdd) layer and a ground (Gnd) layer, and the ceramic package further comprises:

a ground (Gnd) layer, disposed on an opposite side of the signal layer relative to the reference mesh layer, wherein the Gnd layer comprises a second reference mesh plane that is also configured according to the hybrid mesh scheme; and

a plurality of ground (Gnd) vias extending through the mesh planes and coupled to the Gnd layer.

3. The multi-layered ceramic package of claim 1, wherein the reference mesh layer is a Vdd layer and all Vdd traces in the other areas of the Vdd layer run parallel to adjacent signal lines of the signal layer, and wherein the parallel, adjacent Vdd traces reduces discontinuity on the return path and results in less far end (FE) crosstalk.

4. The multi-layered ceramic package of claim 2, wherein the reference mesh layer is a Vdd layer and the ceramic package further comprises:

a plurality of Vdd vias extending trough the reference mesh planes and coupled to the Vdd layer;

wherein a Vdd mesh trace of the Vdd reference mesh that is adjacent to a parallel signal line in the signal layer that is not in a HPU are is coupled to one or more Vdd vias that is close to the Vdd mesh trace;

wherein each parallel Vdd trace and Gnd trace adjacent to a single line that is not in the at least one HPU areas is coupled to a corresponding Vdd via or Gnd via that surrounds the signal line to close a return path.

5. The multi-layered ceramic package of claim 2, wherein further the hybrid mesh scheme comprises:

a first set of Vdd and Gnd traces within respective Vdd layer and Gnd layer adjacent to the at least one HPU areas are configured with a first width; and

one or more of a second set of traces corresponding to the Vdd and Gnd traces located in the other areas and running parallel to adjacent signal lines are configured with a second width that is larger than the first width;

wherein the second width is N times larger than the first width, where N is a real number.

6. The multi-layered ceramic package of claim 5, wherein a width of the signal lines and a dielectric material thickness are optimized to obtain a desired impedance of the signal lines.

7. The multi-layered ceramic package of claim 1, further comprising one or more matched impedances coupled to at least a driver side of one or more signal traces to reduce a near end crosstalk within the ceramic package.

8. The multi-layered ceramic package of claim 1, wherein said hybrid mesh scheme further comprises:

a first mesh pitch for Vdd and Gnd traces adjacent to the other areas of the signal layer that are not HPU areas, wherein the first mesh pitch is larger than a second mesh pitch of Vdd and Gnd traces adjacent to the HPU areas and the perimeter edges of the HPU areas;

wherein configuration of a larger mesh pitch for Vdd and Gnd traces adjacent to the other areas substantially reduces far-end noise within the ceramic package.

9. The multi-layered ceramic package of claim 1, wherein the multi-layered ceramic package is a glass-ceramic package.

10. An integrated circuit (IC) manufactured using the multi-layered ceramic package of claim 1, the IC comprising one or more devices or chips attached to the one or more HPU areas.

11. In a fabrication system for a multi-layer ceramic module having at least one signal layer with one or more devices/chips that require power, a method for providing adequate power to the one or more devices/chips while reducing the amount of metal utilized within the module and reducing far end (FE) noise within the module, the method comprising:

identifying one or more high power usage (HPU) areas within the signal layer at which the one or more devices/chips that require power are to be situated;

providing a full dense mesh plane of traces within first areas of a voltage power (Vdd) layer and a ground (Gnd) layer that are adjacent to the HPU areas within the signal layer to support power deliver to the devices/chips on the signal layer; and

providing a low density mesh plane of traces in other areas of the Vdd layer and Gnd layer that are not adjacent to or proximate to the HPU areas within the signal layer.

12. The method of claim 11, wherein the providing a low density mesh plane further comprises providing only Vdd traces and Gnd traces that are parallel to adjacent signals lines running on the signal layer.

13. The method of claim 11, wherein:

identifying the one or more HPU areas comprises differentiating in a Vdd reference plane and in a Gnd reference plane (a) a first HPU area that is directly adjacent to the one or more HPU areas of the signal layer from (b) a second area that is proximate to a perimeter edge of the one or more HPU areas of the signal layer and (c) a third area on the signal layer that is away from the first area and the second area and not proximate to the one or more HPU areas; and

said method further comprises providing a half dense mesh of traces within second areas of the Vdd layer and Gnd layer that are adjacent to and proximate to the perimeter edge of the HPU areas.

14. The method of claim 11, further comprising:

providing a larger width of the Vdd and Gnd traces running parallel to and adjacent to signal lines in the other areas that are not proximate to the one or more HPU areas, wherein the larger width provides wider Vdd and Gnd traces, which reduce the IR drop on the respective traces.

15. The method of claim 14, further comprising providing a matched impedance at a driver side of one or more signal lines to reduce near end (NE) crosstalk.

16. The method of claim 11, further comprising:

reducing an amount of metal loading at areas within the Gnd and Vdd layers that are not adjacent to or proximate to the HPU areas by increasing a mesh pitch between traces on the Vdd layer and Gnd layer in areas that are not directly adjacent to or proximate to the one or more HPU areas, wherein the increasing of the mesh pitch provides a substantial reduction in the far end crosstalk and better bus performance.

17. The method of claim 11, further comprising:

optimizing a width of the signal lines and a dielectric material thickness to obtain a desired impedance of the signal lines; and

increasing the width of the Vdd and Gnd reference traces that are above, below, and adjacent to the signals lines to reduce noise coupling.

18. The method of claim 11, further comprising:

disposing a plurality of vias in spaces provided by the Vdd mesh plane and Gnd mesh plane with each via of the plurality of vias providing one of a Vdd connection or a Gnd connection;

coupling to surrounding Vdd vias and Gnd vias the signal lines that are not proximate to the HPU areas to close the return path; and

running parallel Vdd traces and Gnd traces that are adjacent to the signal lines, wherein providing the parallel, adjacent Vdd and Gnd traces reduces discontinuity on a return path and results in less far end (FE) crosstalk.

19. A computer program product for use in fabrication and design of high speed ceramic packages comprising:

a computer readable medium; and

program code on said computer readable medium that when executed within a data processing device, said program code provides the functionality of;

identifying one or more high power usage (HPU) areas within the signal layer at which the one or more devices/chips that require power are to be situated;

providing a full dense mesh plane of traces within first areas of a voltage power (Vdd) layer and a ground (Gnd) layer that are adjacent to the HPU areas within the signal layer to support power deliver to the devices/chips on the signal layer; and

providing a low density mesh plane of traces in other areas of the Vdd layer and Gnd layer that are not adjacent to or proximate to the HPU areas within the signal layer.

20. The computer program product of claim 19, wherein:

said program code for identifying the one or more areas further comprises code for differentiating in a Vdd reference plane and in a Gnd reference plane (a) a first HPU area that is directly adjacent to the one or more HPU areas of the signal layer from (b) a second area that is proximate to a perimeter edge of the one or more HPU areas of the signal layer and (c) a third area on the signal layer that is away from the first area and the second area and not proximate to the one or more HPU areas; and

said program code further comprises code completing the functionality of providing a half dense mesh of traces within second areas of the Vdd layer and Gnd layer that are adjacent to and proximate to the perimeter edge of the HPU areas.

21. The computer program product of claim 19, said program code further comprising code for completing the functionality of:

reducing an amount of metal loading at areas within the Gnd and Vdd layers that are not adjacent to or proximate to the HPU areas by increasing a mesh pitch between traces on the Vdd layer and Gnd layer in areas that are not directly adjacent to or proximate to the one or more HPU areas, wherein the increasing of the mesh pitch provides a substantial reduction in the far end crosstalk and better bus performance.

22. The computer program product of claim 19, said program code further comprising code for:

optimizing a width of the signal lines and a dielectric material thickness to obtain a desired impedance of the signal lines;

reducing an amount of metal loading at areas within the Gnd and Vdd layers that are not above or below the device/chip in the signal layer, by reducing a width of the Vdd and Gnd traces to a second width; and

increasing the width of the Vdd and Gnd reference traces that are above, below, and adjacent to the signals lines to reduce noise coupling.

23. The computer program product of claim 19, said program code further comprising code for:

optimizing a width of the signal lines and a dielectric material thickness to obtain a desired impedance of the signal lines; and

increasing the width of the Vdd and Gnd reference traces that are above, below, and adjacent to the signals lines to reduce noise coupling.

24. The computer program product of claim 19, wherein the program code for providing a low density mesh plane further comprises:

providing only Vdd traces and Gnd traces that are parallel to adjacent signals lines running on the signal layer; and

providing a larger width of the Vdd and Gnd traces running parallel to and adjacent to signal lines in the other areas that are not proximate to the one or more HPU areas, wherein the larger width provides wider Vdd and Gnd traces, which reduce the IR drop on the respective traces.

25. The computer program product of claim 24, said program code further comprising code for providing a matched impedance at a driver side of one or more signal lines to reduce near end (NE) crosstalk.