RESISTIVE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME

• US 20110133148A1
• Filed: 05/04/2010
• Published: 06/09/2011
• Est. Priority Date: 12/04/2009
• Status: Active Grant

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: CHOI, Sung-Yool
• Granted Patent: US 8,344,344 B2
• Time in Patent Office: Days
• US Class Current: 257/2
• CPC Class Codes: H10B 63/00 Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• CPC Class Codes: H10N 70/00 Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching integrated devices or assemblies of multiple devices H10N79/00

Abstract

Provided are resistive memory devices and methods of fabricating the same. The resistive memory devices and the methods are advantageous for high integration because they can provide a multilayer memory cell structure. Also, the parallel conductive lines of adjacent layers do not overlap each other in the vertical direction, thus reducing errors in program/erase operations.

Claims

1. A resistive memory device comprising:

a substrate;

first conductive lines disposed over the substrate to be parallel to each other and extend in a first direction;

second conductive lines disposed over the first conductive lines to be parallel to each other and extend in a second direction across the first direction;

third conductive lines disposed over the second conductive lines to be parallel to each other and extend in the first direction;

a first data storage layer disposed between the first conductive line and the second conductive line; and

a second data storage layer disposed between the second conductive line and the third conductive line,

wherein the third conductive line does not overlap the first conductive line in the vertical direction.

2. The resistive memory device of claim 1, further comprising fourth conductive lines disposed over the third conductive lines to be parallel to each other and extend in the second direction,

wherein the fourth conductive line does not overlap the second conductive line in the vertical direction.

3. The resistive memory device of claim 2, further comprising:

n^th conductive lines disposed over the fourth conductive lines to be insulated from the fourth conductive lines and extend in the first direction; and

(n+1)^th conductive lines disposed over the n^th conductive lines to be insulated from the n^th conductive lines and extend in a third direction,

wherein ‘

n’

is a natural number greater than or equal to 5, one of the n^th conductive lines overlaps the first conductive line in the vertical direction, and one of the (n+1)^th conductive lines overlaps the second conductive line in the vertical direction.

4. The resistive memory device of claim 1, wherein the first and second data storage layers comprise a metal oxide layer containing a first metal.

5. The resistive memory device of claim 4, wherein the first to third conductive lines comprise a second metal that has a higher oxygen affinity than the first metal of the first and second data storage layers.

6. The resistive memory device of claim 5, wherein the first to third conductive lines comprise aluminum or an alkali metal.

7. The resistive memory device of claim 1, wherein the first and second data storage layers comprise a material that reacts with one of the first to third conductive lines to form an oxide layer.

8. The resistive memory device of claim 7, wherein the thickness of the oxide layer varies by a voltage applied to at least one of the conductive lines.

9. The resistive memory device of claim 7, wherein the number of charge trap sites in the first and second data storage layers varies by the voltage applied to at least one of the conductive lines.

10. The resistive memory device of claim 1, wherein the first and second data storage layers cover an entire surface of the substrate.

11. The resistive memory device of claim 1, wherein the first data storage layer is disposed at the intersection of the first conductive line and the second conductive line, and the second data storage layer is disposed at the intersection of the second conductive line and the third conductive line.

12. The resistive memory device of claim 11, wherein the first and second data storage layers comprise an N-type metal oxide, and the resistive memory device further comprises:

a first P-type pattern disposed between the first data storage layer and the first conductive line; and

a second P-type pattern disposed between the second data storage layer and the second conductive line.

13. The resistive memory device of claim 1, further comprising:

a first diffusion barrier layer disposed between the first data storage layer and the first conductive line; and

a second diffusion barrier layer disposed between the second data storage layer and the second conductive line.

14. The resistive memory device of claim 1, wherein the first and second data storage layers have a plurality of conductive states according to a voltage applied to at least one of the conductive lines.

15. A method of fabricating a resistive memory device, comprising:

forming first conductive lines over a substrate such that the first conductive lines are parallel to each other and extend in a first direction;

forming a first data storage layer on the first conductive lines;

forming second conductive lines on the first data storage layer such that the second conductive lines are parallel to each other and extend in a second direction across the first direction;

forming a second data storage layer on the second conductive lines; and

forming third conductive lines on the second data storage layer such that the third conductive lines are parallel to each other and extend in the first direction,

wherein the third conductive line does not overlap the first conductive line in the vertical direction.

16. The method of claim 15, wherein the first and second data storage layers comprise a metal oxide layer containing a first metal.

17. The method of claim 16, wherein the second and third conductive lines comprise a second metal that has a higher oxygen affinity than the first metal of the first and second data storage layers.

18. The method of claim 15, wherein the first and second data storage layers react with the second and third conductive lines to form an oxide layer.

19. The method of claim 18, wherein the oxide layer is formed simultaneously with the forming of the second and third conductive lines.

20. The method of claim 15, further comprising:

forming a third data storage layer on the third conductive lines; and

forming fourth conductive lines on the third data storage layer such that the fourth conductive lines are parallel to each other and extend in the second direction,

wherein the fourth conductive line does not overlap the second conductive line in the vertical direction.