Semiconductor Element, Semiconductor Device, And Method For Manufacturing The Same

• US 20110133177A1
• Filed: 11/30/2010
• Published: 06/09/2011
• Est. Priority Date: 12/04/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kurata, Motomu, Mikami, Mayumi, Suzawa, Hideomi
• Granted Patent: US 8,501,564 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 2029/42388 characterised by the shape of the insulating material
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/12 characterised by the materials of which they are formed
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

The semiconductor element includes an oxide semiconductor layer on an insulating surface; a source electrode layer and a drain electrode layer over the oxide semiconductor layer; a gate insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating layer. The source electrode layer and the drain electrode layer have sidewalls which are in contact with a top surface of the oxide semiconductor layer.

Claims

1. A semiconductor element comprising:

a semiconductor layer over an insulating surface;

a source electrode layer and a drain electrode layer on the semiconductor layer;

sidewalls provided in direct contact with a side surface of the source electrode layer and a side surface of the drain electrode layer;

a gate insulating layer over the semiconductor layer, the sidewalls, the source electrode layer, and the drain electrode layer; and

a gate electrode layer on the gate insulating layer,

wherein the sidewalls are provided between the gate insulating layer and the source electrode layer and the drain electrode layer, and

wherein the sidewalls and the gate electrode layer overlap at least partly with each other.

2. The semiconductor element according to claim 1, further comprising:

a conductive layer on the insulating surface; and

an insulating layer covering the conductive layer,

wherein the conductive layer overlaps with the semiconductor layer with the insulating layer interposed therebetween.

3. The semiconductor element according to claim 1,

wherein the gate insulating layer and an insulating layer are provided between the gate electrode layer and the source electrode layer or the drain electrode layer, and

wherein the source electrode layer or the drain electrode layer overlaps with a part of the gate electrode layer with the gate insulating layer and the insulating layer interposed therebetween.

4. The semiconductor element according to claim 1,

wherein the sidewalls comprise an insulating material.

5. A semiconductor device comprising the semiconductor element according to claim 1,

wherein the semiconductor device is an electronic device selected from the group consisting of a laptop personal computer, a portable information terminal, an e-book reader, a mobile phone, and a digital camera.

6. The semiconductor element according to claim 1,

wherein the semiconductor layer is an oxide semiconductor layer.

7. A semiconductor element comprising:

an oxide semiconductor layer over an insulating surface;

a source electrode layer and a drain electrode layer on the oxide semiconductor layer;

sidewalls provided in direct contact with a side surface of the source electrode layer and a side surface of the drain electrode layer;

a gate insulating layer over the oxide semiconductor layer, the sidewalls, the source electrode layer, and the drain electrode layer; and

a gate electrode layer on the gate insulating layer,

wherein the sidewalls are provided between the gate insulating layer and the source electrode layer and the drain electrode layer,

wherein the sidewalls and the gate electrode layer overlap at least partly with each other, and

wherein the sidewalls are in direct contact with a top surface of the oxide semiconductor layer.

8. The semiconductor element according to claim 7, further comprising:

a conductive layer on the insulating surface; and

an insulating layer covering the conductive layer,

wherein the conductive layer overlaps with the oxide semiconductor layer with the insulating layer interposed therebetween.

9. The semiconductor element according to claim 7,

wherein the sidewalls comprise an insulating material.

10. A semiconductor device comprising the semiconductor element according to claim 7,

wherein the semiconductor device is an electronic device selected from the group consisting of a laptop personal computer, a portable information terminal, an e-book reader, a mobile phone, and a digital camera.

11. The semiconductor element according to claim 7, wherein a carrier concentration in the oxide semiconductor layer is lower than 1×

10¹²/cm³.

12. The semiconductor element according to claim 7, wherein an off-state current of the semiconductor element is less than 1×

10<sup>−

13</sup> A.

13. A semiconductor element comprising:

an oxide semiconductor layer over an insulating surface;

a source electrode layer and a drain electrode layer on the oxide semiconductor layer,

wherein the source electrode layer comprising;

a first source electrode layer; and

a second source electrode layer on the first source electrode layer,

wherein the drain electrode layer comprising;

a first drain electrode layer; and

a second drain electrode layer on the first drain electrode layer,

a first sidewall provided in direct contact with a side surface of the second source electrode layer and a top surface of the first source electrode layer,

a second sidewall provided in direct contact with a side surface of the second drain electrode layer and a top surface of the first drain electrode layer,

a gate insulating layer over the oxide semiconductor layer, the first sidewall, the second sidewall, the source electrode layer, and the drain electrode layer; and

a gate electrode layer on the gate insulating layer,

wherein the first sidewall and the second sidewall are provided between the gate insulating layer and the source electrode layer and the drain electrode layer,

wherein the first sidewall and the gate electrode layer overlap at least partly with each other,

wherein the second sidewall and the gate electrode layer overlap at least partly with each other,

wherein the first source electrode layer extends beyond an edge of the second source electrode layer, and

wherein the first drain electrode layer extends beyond an edge of the second drain electrode layer.

14. The semiconductor element according to claim 13,

wherein the gate insulating layer and an insulating layer are provided between the gate electrode layer and the source electrode layer or the drain electrode layer, and

wherein the source electrode layer or the drain electrode layer overlaps with a part of the gate electrode layer with the gate insulating layer and the insulating layer interposed therebetween.

15. The semiconductor element according to claim 13,

wherein the first sidewall and the second sidewall each comprise an insulating material.

16. A semiconductor device comprising the semiconductor element according to claim 13,

wherein the semiconductor device is an electronic device selected from the group consisting of a laptop personal computer, a portable information terminal, an e-book reader, a mobile phone, and a digital camera.

17. The semiconductor element according to claim 13, wherein a carrier concentration in the oxide semiconductor layer is lower than 1×

10¹²/cm³.

18. The semiconductor element according to claim 13, wherein an off-state current of the semiconductor element is less than 1×

10<sup>−

13</sup> A.

19. A semiconductor device comprising:

an EDMOS circuit comprising, on an insulating surface, a first semiconductor element including a first oxide semiconductor layer and a second semiconductor element including a second oxide semiconductor layer,

wherein the first oxide semiconductor layer and the second oxide semiconductor layer has a carrier concentration of lower than 1×

10¹²/cm³.

20. A method for manufacturing a semiconductor element, comprising the steps of:

forming a semiconductor layer over an insulating surface;

forming a source electrode layer and a drain electrode layer on the semiconductor layer;

forming a film serving as sidewalls on the semiconductor layer, the source electrode layer, and the drain electrode layer;

forming sidewalls by etching the film serving as the sidewalls, the sidewalls being in direct contact with a side surface of the source electrode layer and a side surface of the drain electrode layer;

forming a gate insulating layer over the semiconductor layer, the source electrode layer, the drain electrode layer, and the sidewalls; and

forming a gate electrode layer over the gate insulating layer so that the gate electrode layer overlaps with the sidewalls at least partly.

21. The method for manufacturing the semiconductor element according to claim 20, further comprising the steps of:

forming a conductive layer on the insulating surface; and

forming an insulating layer covering the conductive layer,

wherein the conductive layer overlaps with the semiconductor layer with the insulating layer interposed therebetween.

22. The semiconductor element according to claim 20,

wherein the sidewalls comprise an insulating material.

23. A method for manufacturing a semiconductor element, comprising the steps of:

forming an oxide semiconductor layer over an insulating surface;

forming a source electrode layer and a drain electrode layer on the oxide semiconductor layer;

forming a film serving as sidewalls on the oxide semiconductor layer, the source electrode layer, and the drain electrode layer;

forming sidewalls by etching the film serving as the sidewalls, the sidewalls being in direct contact with a side surface of the source electrode layer, a side surface of the drain electrode layer, and a top surface of the oxide semiconductor layer;

forming a gate insulating layer over the oxide semiconductor layer, the source electrode layer, the drain electrode layer, and the sidewalls; and

forming a gate electrode layer over the gate insulating layer so that the gate electrode layer overlaps with the sidewalls at least partly.

24. The method for manufacturing the semiconductor element according to claim 23, further comprising the steps of:

forming a conductive layer on the insulating surface; and

forming an insulating layer covering the conductive layer,

wherein the conductive layer overlaps with the oxide semiconductor layer with the insulating layer interposed therebetween.

25. The semiconductor element according to claim 23,

wherein the sidewalls comprise an insulating material.

26. A method for manufacturing a semiconductor element, comprising the steps of:

forming an oxide semiconductor layer over an insulating surface;

forming a first conductive film and a second conductive film on the oxide semiconductor layer;

forming a second source electrode layer and a second drain electrode layer by etching the second conductive film;

forming a film serving as sidewalls on the first conductive film, the second source electrode layer, and the second drain electrode layer;

forming sidewalls by etching the film serving as the sidewalls, the sidewalls being in direct contact with a side surface of the second source electrode layer and a side surface of the second drain electrode layer;

forming a first source electrode layer and a first drain electrode layer by etching the first conductive film using the sidewalls as masks so that the sidewalls are in direct contact with top surfaces of the first source electrode layer and the first drain electrode layer, the first source electrode layer extending beyond an edge of the second source electrode layer, and the first drain electrode layer extending beyond an edge of the second drain electrode layer;

forming a gate insulating layer over the oxide semiconductor layer, the first source electrode layer, the second source electrode layer, the first drain electrode layer, the second drain electrode layer, and the sidewalls; and

forming a gate electrode layer over the gate insulating layer so that the gate electrode layer overlaps with the sidewalls at least partly.

27. The method for manufacturing the semiconductor element according to claim 26,

wherein the gate insulating layer and an insulating layer are provided between the gate electrode layer and the second source electrode layer or the second drain electrode layer, and

wherein the second source electrode layer or the second drain electrode layer overlaps with a part of the gate electrode layer with the gate insulating layer and the insulating layer interposed therebetween.

28. The semiconductor element according to claim 26,

wherein the sidewalls comprise an insulating material.