SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20110133191A1
• Filed: 12/01/2010
• Published: 06/09/2011
• Est. Priority Date: 12/04/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei
• Granted Patent: US 8,624,245 B2
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device includes an oxide semiconductor layer including a crystalline region over an insulating surface, a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer over the gate insulating layer in a region overlapping with the crystalline region. The crystalline region includes a crystal whose c-axis is aligned in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

Claims

1. A semiconductor device comprising:

an oxide semiconductor layer including a crystalline region over an insulating surface;

a source electrode layer and a drain electrode layer in electrical contact with the oxide semiconductor layer;

a gate insulating layer covering the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and

a gate electrode layer over the crystalline region with the gate insulating layer interposed therebetween,

wherein the crystalline region includes a crystal whose c-axis is aligned in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

2. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises a depression portion.

3. The semiconductor device according to claim 1, further comprising insulating layers having substantially same shapes as the source electrode layer and the drain electrode layer, over the source electrode layer and the drain electrode layer respectively.

4. The semiconductor device according to claim 1, wherein a portion of the source electrode layer and the drain electrode layer in contact with the oxide semiconductor layer comprises a material having low oxygen affinity.

5. The semiconductor device according to claim 1, wherein a region other than the crystalline region in the oxide semiconductor layer has an amorphous structure.

6. The semiconductor device according to claim 1, wherein a difference in height of the surface of the oxide semiconductor layer is 1 nm or less in a region overlapping with the gate electrode layer.

7. A semiconductor device comprising:

a first gate electrode layer over an insulating surface;

a first gate insulating layer covering the first gate electrode layer;

an oxide semiconductor layer including a crystalline region over the first gate insulating layer;

a source electrode layer and a drain electrode layer in electrical contact with the oxide semiconductor layer;

a second gate insulating layer covering the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and

a second gate electrode layer over the crystalline region with the second gate insulating layer interposed therebetween,

wherein the crystalline region includes a crystal whose c-axis is aligned in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

8. The semiconductor device according to claim 7, wherein the oxide semiconductor layer comprises a depression portion.

9. The semiconductor device according to claim 7, further comprising insulating layers having substantially same shapes as the source electrode layer and the drain electrode layer, over the source electrode layer and the drain electrode layer respectively.

10. The semiconductor device according to claim 7, wherein a portion of the source electrode layer and the drain electrode layer in contact with the oxide semiconductor layer comprises a material having low oxygen affinity.

11. The semiconductor device according to claim 7, wherein a region other than the crystalline region in the oxide semiconductor layer has an amorphous structure.

12. A manufacturing method of a semiconductor device, comprising:

forming an oxide semiconductor layer over an insulating surface;

forming a conductive layer over the oxide semiconductor layer;

forming a source electrode layer and a drain electrode layer by etching the conductive layer;

forming a crystalline region in the oxide semiconductor layer by performing heat treatment to align c-axis of the crystalline region in a direction substantially perpendicular to a surface of the oxide semiconductor layer;

forming a gate insulating layer so as to cover the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and

forming a gate electrode layer over the gate insulating layer in a region overlapping with the crystalline region.

13. The manufacturing method of a semiconductor device according to claim 12, wherein the heat treatment is performed at a temperature higher than or equal to 550°

C. and lower than or equal to 850°

C.

14. The manufacturing method of a semiconductor device according to claim 12, wherein a part of the oxide semiconductor layer is removed when the conductive layer is etched.

15. The manufacturing method of a semiconductor device according to claim 12, further comprising the step of forming insulating layers having substantially same shapes as the source electrode layer and the drain electrode layer over the source electrode layer and the drain electrode layer respectively.

16. The manufacturing method of a semiconductor device according to claim 12, wherein a portion of the source electrode layer and the drain electrode layer in contact with the oxide semiconductor layer is formed using a material having low oxygen affinity.

17. The manufacturing method of a semiconductor device according to claim 12, wherein an oxide semiconductor layer having an amorphous structure is formed as the oxide semiconductor layer, and the amorphous structure remains in a region other than the crystalline region.

18. A manufacturing method of a semiconductor device, comprising:

forming a first gate electrode layer over an insulating surface;

forming a first gate insulating layer so as to cover the first gate electrode layer;

forming an oxide semiconductor layer over the first gate insulating layer;

forming a conductive layer over the oxide semiconductor layer;

forming a source electrode layer and a drain electrode layer by etching the conductive layer;

forming a crystalline region in the oxide semiconductor layer by performing heat treatment to align c-axis of the crystalline region in a direction substantially perpendicular to a surface of the oxide semiconductor layer;

forming a second gate insulating layer so as to cover the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and

forming a second gate electrode layer over the second gate insulating layer in a region overlapping with the crystalline region.

19. The manufacturing method of a semiconductor device according to claim 18, wherein the heat treatment is performed at a temperature higher than or equal to 550°

C. and lower than or equal to 850°

C.

20. The manufacturing method of a semiconductor device according to claim 18, wherein a part of the oxide semiconductor layer is removed when the conductive layer is etched.

21. The manufacturing method of a semiconductor device according to claim 18, further comprising the step of forming insulating layers having substantially same shapes as the source electrode layer and the drain electrode layer over the source electrode layer and the drain electrode layer respectively.

22. The manufacturing method of a semiconductor device according to claim 18, wherein a portion of the source electrode layer and the drain electrode layer in contact with the oxide semiconductor layer is formed using a material having low oxygen affinity.

23. The manufacturing method of a semiconductor device according to claim 18, wherein an oxide semiconductor layer having an amorphous structure is formed as the oxide semiconductor layer, and the amorphous structure remains in a region other than the crystalline region.