SHIELDED GATE TRENCH MOSFET WITH INCREASED SOURCE-METAL CONTACT

• US 20110133258A1
• Filed: 01/28/2011
• Published: 06/09/2011
• Est. Priority Date: 08/14/2009
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Chen, John
• Granted Patent: US 8,618,601 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor device formed on a semiconductor substrate having a substrate top surface, includes: a gate trench extending from the substrate top surface into the semiconductor substrate; a gate electrode in the gate trench; a dielectric material disposed over the gate electrode; a body region adjacent to the gate trench; a source region embedded in the body region, at least a portion of the source region extending above the dielectric material; a contact trench that allows contact such as electrical contact between the source region and the body region; and a metal layer disposed over at least a portion of a gate trench opening, at least a portion of the source region, and at least a portion of the contact trench.

Claims

1-1. he semiconductor device of claim 1, wherein the source region has a substantially vertical surface, and at least a portion of the substantially vertical surface is in physical contact with the metal layer.

11. A method for fabricating a semiconductor device, comprising:

forming a gate trench;

forming a gate electrode within the gate trench;

forming a gate top dielectric material over the top of the gate electrode;

forming a body region and a source region;

forming a contact trench;

etching back the gate top dielectric material such that at least a portion of the source is region extends above the gate top dielectric material; and

depositing a metal layer over at least a portion of a gate trench opening, at least a portion of the source region, and at least a portion of the contact trench.

14. The method of claim 11, wherein etching back the gate top dielectric material and depositing the metal layer are performed such that the metal layer covers the gate top dielectric material over the gate electrode and contacts a sidewall of the source region facing the gate top dielectric material.

15. The method of claim 11, wherein the gate top dielectric material is recessed below the substrate top surface.

16. The method of claim 11, wherein the source region has a substantially vertical surface, and at least a portion of the substantially vertical surface is in physical contact with the metal layer.

17. The method of claim 11, wherein the gate trench has a trench wall that is at least in part curved.

18. The method of claim 17, wherein the source region has a surface that at least in part conforms to the curved portion of the trench wall.

19. The method of claim 11, wherein the metal layer is in contact with the source region on multiple sides.

20. The method of claim 11, wherein the metal layer is in contact with the source region on a side of the source region facing the contact trench and on a side of the source region facing the gate top dielectric material.

21. The method of claim 11, further comprising disposing a conductive plug at least in part within the contact trench.

22. The method of claim 11, wherein the metal layer forms a conductive plug that is at least in part within the contact trench.

12-2. he method of claim 12, further comprising forming an inter-electrode dielectric between the shield electrode and the gate electrode.