SYSTEM AND METHOD FOR EEPROM ARCHITECTURE
First Claim
1. A method of manufacturing an Electrically Erasable Programmable Read-Only Memory (EEPROM), the method comprising:
- providing a semiconductor substrate having an active region;
forming a gate oxide layer overlying the semiconductor substrate;
providing a first mask overlaying the gate oxide layer, the first mask defining a tunnel gate opening;
selectively etching the gate oxide layer using the first mask to form a tunnel oxide layer;
depositing a first polysilicon layer overlying the gate oxide layer and the tunnel oxide layer;
etching the first polysilicon layer to obtain a floating gate structure and a selective gate structure, the floating gate structure having a top and a first side and a second side, and the selective gate structure having a third side and a fourth side;
angle doping the floating gate structure with a first dopant at a first dose and a first energy level to obtain a first doped region and a second doped region;
forming a dielectric layer structure overlying the gate oxide layer, the tunnel oxide layer, the selective gate structure, and the top and the first and second sides of the floating gate structure;
removing the dielectric layer except a portion covering the top and the first and second sides of the floating gate structure;
depositing a second polysilicon layer overlying the portion of the dielectric layer structure covering the top and the first and second sides of the floating gate structure to form a control gate structure; and
angle doping the selective gate of the selective gate with a second dopant at a second dose and a second energy level to obtain a third doped region;
wherein the first doped and second doped partially extend underneath the first and the second sides of the floating gates,wherein the third doped region partially overlaps the second doped region.
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Abstract
A method for manufacturing an Electrically Erasable Programmable Read-Only Memory (EEPROM) device includes providing a substrate and forming a gate oxide over the substrate. Also, the method includes providing a mask overlying the gate oxide layer, the mask defining a tunnel opening. The method additionally includes performing selective etching over the mask to form a tunnel oxide layer. The method includes forming a floating gate over the tunnel oxide layer and a selective gate over the gate oxide layer. The method includes angle doping a region of the substrate using the floating gate as a mask to obtain a first doped region. The method further includes forming a dielectric layer over the floating gate and a control gate over the dielectric layer. The method additionally includes angle doping a second region of the substrate using the selective gate as a mask to obtain a second doped region, wherein the first and second doped regions partially overlap.
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Citations
25 Claims
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1. A method of manufacturing an Electrically Erasable Programmable Read-Only Memory (EEPROM), the method comprising:
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providing a semiconductor substrate having an active region; forming a gate oxide layer overlying the semiconductor substrate; providing a first mask overlaying the gate oxide layer, the first mask defining a tunnel gate opening; selectively etching the gate oxide layer using the first mask to form a tunnel oxide layer; depositing a first polysilicon layer overlying the gate oxide layer and the tunnel oxide layer; etching the first polysilicon layer to obtain a floating gate structure and a selective gate structure, the floating gate structure having a top and a first side and a second side, and the selective gate structure having a third side and a fourth side; angle doping the floating gate structure with a first dopant at a first dose and a first energy level to obtain a first doped region and a second doped region; forming a dielectric layer structure overlying the gate oxide layer, the tunnel oxide layer, the selective gate structure, and the top and the first and second sides of the floating gate structure; removing the dielectric layer except a portion covering the top and the first and second sides of the floating gate structure; depositing a second polysilicon layer overlying the portion of the dielectric layer structure covering the top and the first and second sides of the floating gate structure to form a control gate structure; and angle doping the selective gate of the selective gate with a second dopant at a second dose and a second energy level to obtain a third doped region; wherein the first doped and second doped partially extend underneath the first and the second sides of the floating gates, wherein the third doped region partially overlaps the second doped region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of manufacturing an Electrically Erasable Programmable Read-Only Memory (EEPROM), the method comprising:
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providing a substrate; forming a gate oxide over a first region of the substrate; forming a tunnel oxide over a second region of the substrate; forming a floating gate over the tunnel oxide; forming a selective gate over the gate oxide; angle doping the first region of the substrate having the floating gate to obtain a first doped region within the substrate; forming a dielectric layer structure over the floating gate; and forming a control gate over the dielectric layer structure; wherein the gate oxide and the tunnel oxide having a different thickness. - View Dependent Claims (14, 15, 16, 17)
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18. An Electrically Erasable Programmable Read-Only Memory (EEPROM) device comprising:
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a semiconductor substrate having an active region; a tunnel oxide over a first region of the semiconductor substrate; a gate oxide over a second region of the semiconductor substrate; a floating gate over the tunnel oxide, the floating gate having a first side and a second side; a selective gate over the gate oxide, the selective gate having a third side and a fourth side; a dielectric layer over the floating gate and the first and second sides; and a control gate over the dielectric layer; wherein a first portion of the first region of the semiconductor substrate is angle doped with arsenic ions at a dose of about 10E13 ions/cm2 using the floating gate as a mask - View Dependent Claims (19, 20, 21, 22, 23, 24, 25)
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Specification