MEMORY DEVICE WITH RECESSED CONSTRUCTION BETWEEN MEMORY CONSTRUCTIONS
First Claim
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1. A memory device comprising:
- a substrate having a first surface;
a plurality of memory cells arranged in a pattern on the substrate, wherein the plurality of memory cells each include a charge storage device and a recessed access device formed so as to extend into the substrate, wherein the recessed access device induces a first depletion region in the substrate and further defines a current flow path about the recessed perimeter of the recessed access device within the substrate;
a plurality of isolation structures each recessed in the substrate so as to isolate adjacent memory cells of the plurality of memory cells from each other, wherein each of the plurality of isolation structures induce a second depletion region in the substrate to thereby inhibit leakage between adjacent memory cells.
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Abstract
A recessed transistor construction is formed between a first access transistor construction and a second access transistor construction to provide isolation between the access transistor constructions of a memory device. In some embodiments, a gate of the recessed transistor construction is grounded. In an embodiment, the access transistor constructions are recess access transistors. In an embodiment, the memory device is a DRAM. In another embodiment, the memory device is a 4.5F2 DRAM cell.
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Citations
20 Claims
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1. A memory device comprising:
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a substrate having a first surface; a plurality of memory cells arranged in a pattern on the substrate, wherein the plurality of memory cells each include a charge storage device and a recessed access device formed so as to extend into the substrate, wherein the recessed access device induces a first depletion region in the substrate and further defines a current flow path about the recessed perimeter of the recessed access device within the substrate; a plurality of isolation structures each recessed in the substrate so as to isolate adjacent memory cells of the plurality of memory cells from each other, wherein each of the plurality of isolation structures induce a second depletion region in the substrate to thereby inhibit leakage between adjacent memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A memory device comprising:
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a substrate having a first surface; a first memory construction comprising; a first memory storage device; a first digit line; and a first transistor construction having a first recessed gate that extends into the substrate from the first surface, a first source, and a first drain, wherein the first memory storage device is electrically coupled to the first source, and the first digit line is electrically coupled to the first drain; a second memory construction comprising; a second memory storage device; a second digit line; and a second transistor construction having a second recessed gate, a second source, and a second drain, wherein the second memory storage device is electrically coupled to the second source, and the second digit line is electrically coupled to the second drain; wherein the first and second transistor constructions are recessed access devices; and a grounded recessed transistor gate construction interposed between the first and second memory constructions. - View Dependent Claims (11, 12, 13, 14)
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15. A memory device comprising:
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a substrate having a first surface; a first memory construction comprising; a first transistor construction having a first recessed gate that extends into the substrate from the first surface; a first source; and a first drain, the first recessed gate interposed between the first source and the first drain; a second memory construction comprising; a second transistor construction having a second recessed gate that extends into the substrate from the first surface; a second source; and a second drain, the second recessed gate interposed between the second source and the second drain; and a recessed transistor gate construction interposed between the first and second memory constructions, wherein the recessed transistor gate construction is biased so as not to electrically conduct between the first and the second transistor constructions. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification