Trench MOS Device with Schottky Diode and Method for Manufacturing Same

• US 20110133271A1
• Filed: 12/03/2009
• Published: 06/09/2011
• Est. Priority Date: 12/03/2009
• Status: Active Grant

• Current Assignee: Chiao-Shun Chuang
• Original Assignee: Diodes Taiwan, Inc. (Diodes Incorporated)
• Inventors: Chuang, Chiao-Shun
• Granted Patent: US 8,368,140 B2
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

In one embodiment the present invention includes a semiconductor device. The semiconductor device comprises a first semiconductor region, a second semiconductor region and a trench region. The first semiconductor region is of a first conductivity type and a first conductivity concentration. The trench region includes a metal layer in contact with the first semiconductor region to form a metal-semiconductor junction. The second semiconductor region is adjacent to the first semiconductor region that has a second conductivity type and a second conductivity concentration. The second semiconductor region forms a PN junction with the first semiconductor region, and the trench region has a depth such that the metal-semiconductor junction is proximate to the PN junction.

Claims

1. A semiconductor device comprising:

a first semiconductor region of a first conductivity type and a first conductivity concentration;

a first trench including a metal layer in contact with said first semiconductor region to form a metal-semiconductor junction; and

a second semiconductor region adjacent to said first semiconductor region and the metal-semiconductor junction, the second semiconductor region having a second conductivity type and a second conductivity concentration,

wherein said second semiconductor region forms a PN junction with said first semiconductor region.

2. The semiconductor device of claim 1 further comprising a second trench and a conductive material within said second trench,

wherein said second semiconductor region is between said first and second trenches.

3. The semiconductor device of claim 2 further comprising a dielectric layer between said conductive material and said second semiconductor region,

wherein said conductive material and said dielectric layer form a gate within said trench which, when biased, creates an inversion layer within said second semiconductor layer.

4. The semiconductor device of claim 2 wherein a depth of said second trench is greater than a depth of said first trench, and wherein said PN junction curves upward from an intersection with said second trench to an intersection with said first trench.

5. The semiconductor device of claim 3 further comprising a third semiconductor region of said first semiconductor type,

wherein said third semiconductor region is adjacent to said second semiconductor region and said first trench, and wherein the first semiconductor region, the second semiconductor region, third semiconductor region, said dielectric layer, and said conductive material form a trench MOS device.

6. The semiconductor device of claim 1 further comprising a third semiconductor region of said second semiconductor type adjacent to the second semiconductor region and the first trench,

wherein said third semiconductor region defines a width in which said metal layer is in contact with said first semiconductor region.

7. The semiconductor device of claim 1 further comprising a third semiconductor region of said second semiconductor type and said second semiconductor concentration,

wherein said third semiconductor region forms a PN junction with said first semiconductor region, and

wherein said trench is between said second semiconductor region and said third semiconductor region.

8. A method comprising:

forming a first semiconductor region of a first conductivity type and a first conductivity concentration within a second semiconductor region of a second conductivity type and a second conductivity concentration;

etching a first trench through said first semiconductor region; and

adding a metal layer within said first trench such that said metal layer contacts said second semiconductor region to form a metal-semiconductor junction;

wherein said first semiconductor region forms a PN junction with said second semiconductor region, and

wherein said first trench has a depth such that said metal-semiconductor junction is adjacent to said PN junction.

9. The method of claim 8 further comprising:

etching a second trench; and

adding a conductive material within said second trench,

wherein said first semiconductor region is between said first and second trench regions.

10. The method of claim 9 further comprising:

adding a dielectric layer between said conductive material and said first semiconductor region,

wherein said conductive material and said dielectric layer form a gate within said trench which, when biased, creates an inversion layer within said first semiconductor region.

11. The method of claim 9 wherein a depth of said second trench is greater than said depth of said first trench, and wherein said forming said first semiconductor region includes forming a curved boundary such that said PN junction curves upward from an intersection with said second trench to an intersection with said first trench.

12. The method of claim 8 further comprising:

forming a third semiconductor region of said second semiconductor type,

wherein said third semiconductor region is above said first semiconductor region and adjacent to said first trench, and wherein said third semiconductor concentration is greater than said first semiconductor concentration.

13. The method of claim 12 further comprising:

forming a fourth semiconductor region of said first semiconductor type adjacent to the first semiconductor region and the first trench to extend the PN junction and reduce the width of the metal-semiconductor junction.