SEMICONDUCTOR DEVICE WITH IMPROVED ON-RESISTANCE

• US 20110133272A1
• Filed: 12/09/2009
• Published: 06/09/2011
• Est. Priority Date: 12/09/2009
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Berger, Rudolf, Schulze, Hans-Joachim, Hirler, Franz, Mauder, Anton, Siemieniec, Ralf
• Granted Patent: US 8,198,678 B2
• Time in Patent Office: Days
• US Class Current: 257/335
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a source, a drain, and a gate configured to selectively enable a current to pass between the source and the drain. The semiconductor device includes a drift zone between the source and the drain and a first field plate adjacent the drift zone. The semiconductor device includes a dielectric layer electrically isolating the first field plate from the drift zone and charges within the dielectric layer close to an interface of the dielectric layer adjacent the drift zone.

Claims

1. A semiconductor device comprising:

a source;

a drain;

a gate configured to selectively enable a current to pass between the source and the drain;

a drift zone between the source and the drain;

a doped semiconductor substrate between the drift zone and the drain;

a first field plate adjacent the drift zone;

a dielectric layer electrically isolating the first field plate from the drift zone, the dielectric layer extending into the doped semiconductor substrate; and

charges within the dielectric layer close to an interface of the dielectric layer adjacent the drift zone.

2. The semiconductor device of claim 1, wherein the semiconductor device comprises one of an n-channel transistor wherein the charges are positive charges and a p-channel transistor wherein the charges are negative charges.

3. The semiconductor device of claim 1, wherein the dielectric layer is narrower near the source and wider near the drain.

4. The semiconductor device of claim 1, further comprising:

at least a second field plate below the first field plate.

5. The semiconductor device of claim 4, wherein a width of the second field plate is less than a width of the first field plate.

6. A semiconductor device comprising:

a source;

a drain;

a gate configured to selectively enable a current to pass between the source and the drain;

a drift zone between the source and the drain;

a field stop region between the drift zone and the drain;

a first field plate adjacent the drift zone;

a dielectric layer electrically isolating the first field plate from the drift zone, the dielectric layer extending through the field stop region; and

positive charges within the dielectric layer.

7. The semiconductor device of claim 6, wherein the positive charges are provided by electron irradiation of the dielectric layer.

8. The semiconductor device of claim 6, wherein the positive charges are provided by cesium.

9. The semiconductor device of claim 6, wherein the positive charges provide an area charge density of at least 10¹²/cm².

10-26. -26. (canceled)

27. A semiconductor device comprising:

a source region;

a drain;

a gate configured to selectively enable a current to pass between the source region and the drain;

a drift zone between the source region and the drain;

a body region between the drift zone and the source region;

a first dielectric layer electrically isolating the gate from the body region;

a field plate adjacent the drift zone, the field plate tapered such that the field plate is wider near the gate and narrower near the drain;

a second dielectric layer electrically isolating the first field plate from the drift zone, the second dielectric layer gradually increasing in thickness such that the dielectric layer is thinner near the gate and thicker near the drain; and

charges within the second dielectric layer close to an interface of the dielectric layer adjacent the drift zone.

28. The semiconductor device of claim 27, further comprising:

a doped semiconductor substrate contacting the drain; and

a field stop region between the drift zone and the semiconductor substrate.

29. The semiconductor device of claim 28, wherein the second dielectric layer extends through the field stop region and into the doped semiconductor substrate.

30. The semiconductor device of claim 28, wherein the field plate extends through the field stop region and into the doped semiconductor substrate.

31. The semiconductor device of claim 27, wherein the semiconductor device comprises an n-channel transistor wherein the charges are positive charges.

32. The semiconductor device of claim 27, wherein the semiconductor device comprises a p-channel transistor wherein the charges are negative charges.

33. The semiconductor device of claim 27, further comprising:

a body contact region adjacent the source region and contacting the body region.

34. The semiconductor device of claim 33, further comprising:

a source contact directly contacting the source region and the body contact region;

a gate contact directly contacting the gate; and

a third dielectric layer laterally surrounding the source contact and the gate contact.

35. A semiconductor device comprising:

a source region;

a drain;

a gate configured to selectively enable a current to pass between the source region and the drain;

a drift zone between the source region and the drain;

a body region between the drift zone and the source region;

a first dielectric layer electrically isolating the gate from the body region;

a field plate adjacent the drift zone;

a second dielectric layer electrically isolating the first field plate from the drift zone; and

charges within the second dielectric layer close to an interface of the dielectric layer adjacent the drift zone,

wherein the charges are not within the first dielectric layer.

36. The semiconductor device of claim 35, further comprising:

a doped semiconductor substrate contacting the drain; and

a field stop region between the drift zone and the semiconductor substrate.

37. The semiconductor device of claim 36, wherein the second dielectric layer extends through the field stop region and into the doped semiconductor substrate.

38. The semiconductor device of claim 36, wherein the field plate extends through the field stop region and into the doped semiconductor substrate.

39. The semiconductor device of claim 35, wherein the semiconductor device comprises an n-channel transistor wherein the charges are positive charges.

40. The semiconductor device of claim 35, wherein the semiconductor device comprises a p-channel transistor wherein the charges are negative charges.

41. The semiconductor device of claim 35, further comprising:

a body contact region adjacent the source region and contacting the body region.

42. The semiconductor device of claim 41, further comprising:

a source contact directly contacting the source region and the body contact region;

a gate contact directly contacting the gate; and

a third dielectric layer laterally surrounding the source contact and the gate contact.