MULTIPLE DOPING LEVEL BIPOLAR JUNCTIONS TRANSISTORS AND METHOD FOR FORMING

• US 20110133289A1
• Filed: 02/14/2011
• Published: 06/09/2011
• Est. Priority Date: 09/29/2004
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Carroll, Michael Scott, Key, Roger W., Lai, Thiet The, Hamad, Amal Ma, Kerr, Daniel Charles
• Granted Patent: US 8,143,120 B2
• Time in Patent Office: Days
• US Class Current: 257/370
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/66272 Silicon vertical transistors H01L29/66242, H01L29/66257 and H01L29/66265 take precedence

Abstract

A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate. Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors. Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors. According to one embodiment of the present invention, bipolar junction transistors having six different collector dopant densities (and thus six different breakdown characteristics) are formed.

Claims

1. A process for forming bipolar junction transistors in a semiconductor substrate, the process comprising:

forming a first doped tub region of a first dopant type within the substrate;

forming first, second, third and fourth doped sinker regions of a second dopant type within the substrate;

forming second and third tub regions of the second dopant type in the substrate;

concurrently forming first, second, third and fourth subcollector regions and a triple well region all of the second dopant type, wherein the triple well region and the second and the third tub regions cooperate to electrically isolate the first doped tub region from the substrate, and wherein each one of the first, second, third and fourth subcollector region cooperates with a respective one of the first, second, third and fourth doped sinker regions;

doping the second and the fourth subcollector regions with the second dopant type; and

doping a portion of the third and the fourth subcollector regions with the second dopant type.

2. The process of claim 1 further comprising:

forming metal oxide semiconductor field effect transistor structures for cooperating with the first doped tub region and the triple well region to form a metal oxide semiconductor field effect transistor;

forming first bipolar junction transistor structures for cooperating with the first doped sinker region and the first subcollector region to form a first bipolar junction transistor;

forming second bipolar junction transistor structures for cooperating with the second doped sinker region and the second subcollector region to form a second bipolar junction transistor;

forming third bipolar junction transistor structures for cooperating with the third doped sinker region and the third subcollector region to form a third bipolar junction transistor; and

forming fourth bipolar junction transistor structures for cooperating with the fourth doped sinker region and the fourth subcollector region to form a fourth bipolar junction transistor;

wherein the first, second, third and fourth bipolar junction transistors exhibit breakdown characteristics in the following order beginning with the bipolar junction transistor having the highest breakdown voltage, the first bipolar junction transistor, the third bipolar junction transistor, the second bipolar junction transistor and the fourth bipolar junction transistor.

3. The process of claim 2 wherein the metal oxide semiconductor field effect transistor structures comprise a gate structure, and wherein the step of forming the metal oxide semiconductor field effect transistor structures is executed after the step of concurrently forming the first, second, third and fourth subcollector regions and the triple well region and before the step of doping the second and the fourth subcollector regions.

4. The process of claim 3 wherein the step of forming the metal oxide semiconductor field effect transistor structures is executed before the step of doping the second and the fourth subcollector regions.

5. The process of claim 1 wherein the step of concurrently forming the first, second, third, and fourth subcollector regions and the triple well region comprises implanting dopants to form the first, second, third and fourth subcollector regions and the triple well region, and wherein the step of doping the subcollector region further comprises implanting dopants into the subcollector region, and wherein the step of doping a portion of the subcollector region further comprises implanting dopants into the portion of the subcollector region.

6. The process of claim 5 wherein the step of implanting dopants to form the subcollector region and the triple well region further comprises implanting phosphorous at about 1000 keV with a dose of about 2E13 per cubic cm, and wherein the step of implanting dopants into the subcollector region further comprises implanting phosphorous at about 900 keV with a dose of about 5E14 per cubic cm, and wherein the step of implanting dopants into the portion of the subcollector region further comprises implanting phosphorous at about 500 keV with a dose of about 1.5E13.

7. The process of claim 1 further comprising forming material layers overlying the substrate and forming first, second, third and fourth emitter windows within one or more of the material layers, wherein the step of doping the portion of the third and the fourth subcollector regions further comprises doping the portion of the third and the fourth subcollector regions through the third and the fourth emitter window, respectively.

8. A process for forming bipolar junction transistors in a semiconductor substrate further comprising complimentary metal oxide semiconductor field effect transistors, the process comprising:

forming a first doped tub of a first dopant type within the substrate;

forming a second doped tub and a plurality of sinker regions of a second dopant type within the substrate;

forming third and fourth doped tubs of the second doping type in the substrate;

forming a triple well region and a first plurality of subcollector regions comprising a first doping level, wherein the triple well region and the first plurality of subcollector regions are of the second dopant type, and wherein the third and the fourth doped tubs cooperate with the triple well region to electrically isolate the first doped tub from the substrate, and wherein each one of the first plurality of subcollector regions cooperates with one of the plurality of sinker regions;

forming structures associated with the complementary metal oxide semiconductor field effect transistors after forming the triple well region and the first plurality of subcollector regions, wherein one of the structures comprises a gate for each of the complementary metal oxide semiconductor field effect transistors;

doping a first subset of the first plurality of subcollector regions to form a second plurality of subcollector regions comprising a second doping level;

doping a second subset of the first plurality of subcollector regions to form a third plurality of subcollector regions comprising a third doping level; and

doping a subset of the second plurality of subcollector regions to form a fourth plurality of subcollector regions comprising a fourth doping level.

9. The process of claim 8 wherein the bipolar junction transistors exhibit breakdown characteristics in the following order beginning with the bipolar junction transistor having the highest breakdown voltage, according to the doping level of the subcollector, the first doping level, the third doping level, the second doping level and the fourth doping level.

10. An integrated circuit device, comprising:

a semiconductor substrate; and

a BiCMOS block of transistors located on the substrate, comprising;

a plurality of NMOS transistors formed on the semiconductor substrate;

a plurality of PMOS transistors formed on the semiconductor substrate; and

different classes of bipolar junction transistors formed on the semiconductor substrate, wherein each class of the bipolar junction transistors has a different breakdown voltage due to different collector doping densities.

11. A method of fabricating an integrated circuit device, comprising:

forming a BiCMOS block of transistors on a semiconductor substrate, comprising;

forming a plurality of NMOS transistors on the semiconductor substrate;

forming a plurality of PMOS transistors on the semiconductor substrate; and

forming different classes of bipolar junction transistors on the semiconductor substrate, wherein each class of the bipolar junction transistors has a different breakdown voltage due to different collector doping densities.