SEMICONDUCTOR DEVICE WITH OXIDE DEFINE PATTERN

• US 20110133308A1
• Filed: 02/16/2011
• Published: 06/09/2011
• Est. Priority Date: 05/22/2009
• Status: Abandoned Application

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Chan, Kuei-Ti, Marques, Augusto, Lee, Tung-Hsing, Lee, Wen-Chang
• Application Number:
  US13/029,066
• Publication Number:
  US 20110133308A1
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device includes a substrate; an inductor wiring pattern overlying the substrate, wherein the inductor wiring pattern is formed in an inductor-forming region; a plurality of shielding patterns between the inductor wiring pattern and the substrate within the inductor-forming region; and at least one first oxide define (OD) pattern disposed in the substrate or between the inductor wiring pattern and the substrate.

Claims

1. A semiconductor device comprising:

a substrate;

an inductor wiring pattern overlying the substrate, wherein the inductor wiring pattern is formed in an inductor-forming region;

a plurality of shielding patterns between the inductor wiring pattern and the substrate within the inductor-forming region; and

at least one first oxide define (OD) pattern disposed in the substrate or between the inductor wiring pattern and the substrate.

2. The semiconductor device according to claim 1 wherein the semiconductor device further comprises a shallow trench isolation (STI) pattern under the inductor wiring pattern.

3. The semiconductor device according to claim 2 wherein the STI pattern surrounds the OD pattern.

4. The semiconductor device according to claim 2 wherein the shielding patterns is disposed on or over the STI pattern.

5. The semiconductor device according to claim 1 wherein the shielding patterns do not overlap with the OD pattern.

6. The semiconductor device according to claim 1 wherein no dopant is implanted into the OD pattern.

7. The semiconductor device according to claim 1 wherein an N type dopant is implanted into the OD pattern.

8. The semiconductor device according to claim 1 wherein a P type dopant is implanted into the OD pattern.

9. The semiconductor device according to claim 1 wherein no silicide is formed on the OD pattern.

10. The semiconductor device according to claim 1 wherein a dielectric is provided between the substrate and the inductor wiring pattern.

11. The semiconductor device according to claim 1 wherein the OD pattern is disposed in the substrate or between the inductor wiring pattern and the substrate within the inductor-forming region, and wherein a peripheral region is proximate to the inductor-forming region.

12. The semiconductor device according to claim 11 wherein a width of the peripheral region ranges between 0 and 50 micrometers from an edge of the inductor-forming region.

13. The semiconductor device according to claim 11 further comprising at least one second OD pattern disposed in the substrate or between the inductor wiring pattern and the substrate within the peripheral region.

14. The semiconductor device according to claim 11 wherein active devices are formed less than 20 micrometers away from the peripheral region.

15. The semiconductor device according to claim 1 wherein the shielding patterns act as a patterned ground shield.

16. The semiconductor device according to claim 1 wherein the shielding patterns are conductive shielding patterns.

17. The semiconductor device according to claim 1 wherein the shielding patterns are polysilicon shielding patterns.

18. The semiconductor device according to claim 1 wherein the shielding patterns are metal shielding patterns.

19. The semiconductor device according to claim 1 wherein the first OD pattern is further disposed near an active device around the semiconductor device.

20. The semiconductor device according to claim 19 wherein the shielding patterns and a gate of the active device are made of a same layer.