SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

• US 20110133309A1
• Filed: 08/06/2009
• Published: 06/09/2011
• Est. Priority Date: 08/12/2008
• Status: Active Grant

• Current Assignee: ThruChip Japan Inc.
• Original Assignee: KEIO University
• Inventors: Kuroda, Tadahiro
• Granted Patent: US 8,564,093 B2
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48147 with an intermediate bond, e.g. continuous wire daisy chain
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/30107 Inductance

Abstract

The invention relates to a semiconductor device and a manufacturing method for the same, and makes the rejection rate of the product after chips are stacked and mounted sufficiently low, even when the chips are selected in a conventional, simple and inexpensive wafer test.

A first device where a number of first semiconductor chips and a second semiconductor chip for controlling communication between the first semiconductor chips and the outside or communication between the first semiconductor chips are stacked and a second device having at least one third semiconductor chip that communicates with the second semiconductor chip are mounted on a substrate, wherein the third semiconductor chip functions to substitute a first semiconductor chip, there are at least the same number of third semiconductor chips as there are first semiconductor chips that do not operate normally, from among the first semiconductor chips within the first device, and the third semiconductor chips are stacked so as to substitute the functions of the first semiconductor chips that do not operate normally.

Claims

1. A semiconductor device where a first device where a number of first semiconductor chips and a second semiconductor chip for controlling communication between said first semiconductor chips and the outside or communication between said first semiconductor chips are stacked and a second device having at least one third semiconductor chip that communicates with said second semiconductor chip are mounted on a substrate, wherein said third semiconductor chip functions to substitute a first semiconductor chip, there are at least the same number of third semiconductor chips as there are first semiconductor chips that do not operate normally, from among said first semiconductor chips within said first device, and the third semiconductor chips are stacked so as to substitute the functions of said first semiconductor chips that do not operate normally.

2. The semiconductor device according to claim 1, wherein said first semiconductor chips and said second semiconductor chip have a coil for magnetic field communication, so that data is communicated between said first semiconductor chips and said second semiconductor chip, as well as between said first semiconductor chips, as magnetic field communication through inductive coupling of said coils for magnetic field communication, and said first semiconductor chips and said second semiconductor chip are connected to wires for supplying power.

3. The semiconductor device according to claim 2, wherein there are a greater number of said wires for supplying power than determined by the requirement of power consumption.

4. The semiconductor device according to claim 3, wherein each of which said first semiconductor chips has a wire for resetting the communication state of the coil for magnetic field communication provided in the first semiconductor chip and a redundant wire for resetting which functions to substitute said wire for resetting.

5. The semiconductor device according to claim 1, wherein said first semiconductor chips and said third semiconductor chips are semiconductor memory chips.

6. The semiconductor device according to claim 5, wherein said semiconductor memory chips are nonvolatile memories.

7. The semiconductor device according to claim 1, wherein said first semiconductor chips have the same structure.

8. A manufacturing method for a semiconductor device according to which a first device where a number of first semiconductor chips and a second semiconductor chip for controlling communication between said first semiconductor chips and the outside or communication between said first semiconductor chips are stacked is mounted on a substrate, wherein in the case where some of the first semiconductor chips do not operate normally in said first device, a second device where the same number of third semiconductor chips that function to substitute a first semiconductor chip as said first semiconductor chips that do not operate normally are stacked is mounted on said substrate, and said second semiconductor chip and said third semiconductor chips are connected so as to make communication possible between said second semiconductor chip and said third semiconductor chips.