METHOD FOR CONTROLLING AN INTERLEAVING MULTIPHASE REGULATOR AND CORRESPONDING SYSTEM

• US 20110133704A1
• Filed: 06/10/2010
• Published: 06/09/2011
• Est. Priority Date: 06/10/2009
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Zafarana, Alessandro, Zambetti, Osvaldo Enrico
• Granted Patent: US 8,970,195 B2
• Time in Patent Office: Days
• US Class Current: 323/212
• CPC Class Codes: H02M 3/1584 with a plurality of power processing stages connected in parallel

Abstract

A method is provided for controlling turn-on of phases of a multiphase regulator. According to the method, there are tested the conditions necessary for the turn-on of a phase to be turned-on indicated by a first cell of the phase register, and in response to a positive result a corresponding ramp signal is reset. There is then tested the conditions necessary for the turn-on of a phase successive to the phase to be turned on according to the list of priorities of the phase register, and corresponding ramp signals are reset if there is a positive result. In response to no positive results of testing conditions necessary for the turn-on of all phases successive to the phase to be turned on, there is reset a ramp signal corresponding to a phase successive to a last turned on phase indicated by a last cell of the phase register.

Claims

1. A method for controlling turn-on of a plurality of phases of a multiphase regulator of the interleaving type, the phases being turned on by respective modulation signals generated from corresponding ramp signals, and being turned on according to a list of priorities stored by a plurality of cells of a phase register, the method comprising the steps of:

testing conditions necessary for the turn-on of a phase to be turned on that is indicated by a first cell of the phase register;

in response to a positive result of the test of the conditions necessary for the turn-on of a phase to be turned on, resetting a corresponding ramp signal;

after the step of resetting the corresponding ramp signal, testing conditions necessary for the turn-on of a phase successive to the phase to be turned on according to the list of priorities of the phase register, and resetting corresponding ramp signals in response to a positive result of such testing; and

in response to no positive results of testing conditions necessary for the turn-on of all phases successive to the phase to be turned on, forcing reset of a ramp signal corresponding to a phase successive to a last turned on phase that is indicated by a last cell of the phase register, and returning to the step of testing the conditions necessary for the turn-on of a phase to be turned on.

2. The method according to claim 1, wherein the testing of the conditions necessary for the turn-on of a phase comprises determining whether or not a control voltage of that phase is greater than a minimum voltage reference value.

3. The method according to claim 1, wherein the testing of the conditions necessary for the turn-on of a phase comprises determining whether or not a common control voltage is greater than a minimum voltage reference value relative to that phase.

4. The method according to claim 1, wherein the testing of the conditions necessary for the turn-on of a phase comprise updating a further cell indicating the last reset of the phase register by inserting the identifying number of the turned on phase.

5. The method according to claim 4, further comprising:

after the updating, testing the presence or not of a corresponding modulation signal.

6. The method according to claim 5, further comprising:

in response to a positive result of the test of the presence or not of a corresponding modulation signal, updating the phase register by inserting an identifying number of the phase that has been turned on in the last cell of the phase register, and shifting the values contained in the other cells in consequence.

7. The method according to claim 6, wherein the updating of the phase register is not performed if the testing of the conditions necessary for the turn-on of a phase has given a positive result on a last turned-on phase indicated by an identifying number contained in the last cell of the phase register.

8. A modulation system comprising:

a multiphase regulator of the interleaving type having a plurality of phases;

a PWM signal comparator block for the phases; and

a modulator supplying a plurality of ramp signals to the PWM signal comparator block, the modulator comprising control logic for determining a reset sequence of the ramp signals.

9. The modulation system according to claim 8, wherein the modulator further comprises a phase register, the phase register including a plurality of cells storing a list of priorities, each of the cells indicating one of the phases, a first cell indicating a phase to be turned on as determined by the control logic and a last cell indicating a last turned on phase.

10. The modulation system according to claim 9, wherein the control logic updates the cells of the phase register by indicating a phase which is turned on in the last cell and shifting values of the other cells.

11. The modulation system according to claim 8, wherein the modulator includes a plurality of control terminals that receiving a plurality of control voltage signals, the control voltage signals being generated by a current sharing control circuit on the basis of the currents of the phases.

12. The modulation system according to claim 11, wherein the PWM signal comparator comprises one comparator for each of the phases, each of the comparators having a first input terminal connected to a corresponding control terminal of the modulator for receiving a respective control voltage signal, a second input terminal connected to a corresponding output terminal of the modulator for receiving a ramp signal, and an output terminal that supplies one of the modulation signals.

13. The modulation system according to claim 11, wherein the modulator further comprises a plurality of feedback terminals connected to the output terminals of the PWM signal comparator.

14. The modulation system according to claim 8, wherein the modulator further includes a supply terminal connected to a minimum voltage reference corresponding to a minimum voltage value of the modulation signals.

15. The modulation system according to claim 14, wherein the modulator further comprises a ramp signal generator connected to a plurality of output terminals of the control logic and to the minimum voltage reference, the ramp signal generator having a plurality of output terminals that supply the ramp signals.

16. The modulation system according to claim 15, wherein the modulator comprises an input comparator block that includes a plurality of comparators whose number is identical to the number of phases, each of the comparators having a first input terminal connected to a respective control terminal for receiving a control voltage signal, a second input terminal connected to the minimum voltage reference, and an output terminal connected to corresponding input terminals of the control logic.

17. The modulation system according to claim 15, wherein the ramp signal generator comprises one MOS transistor for each of the phases, each of the MOS transistors being coupled in series to a corresponding current generators between a supply voltage reference and the minimum voltage reference, and one of a plurality of capacitors being coupled between one of the output terminals and the minimum voltage reference, each of the MOS transistors having a control terminal connected to at east one of the output terminals of the control logic.

18. The modulation system according to claim 8, wherein the modulator includes a control terminal that receives a common control voltage signal and a plurality of supply terminals connected to a plurality of minimum voltage references obtained from a current sharing control circuit on the basis of the currents of the phases.

19. The modulation system according to claim 18, wherein the modulator comprises an input comparator block that includes a plurality of comparators whose number is identical to the number of phases, each of the comparators having a first input terminal receiving the common control voltage signal, a second input terminal connected to one of the minimum voltage references, and an output terminal connected to corresponding input terminals of the control logic.

20. The modulation system according to claim 19, wherein the ramp signal generator comprises one MOS transistor for each of the phases, each of the MOS transistors being coupled in series to a corresponding current generator between a supply voltage reference and a respective minimum voltage reference, and one of a plurality of capacitors being coupled between a respective output terminal and a respective minimum voltage reference, the MOS transistors having respective control terminals connected to the output terminals of the control logic.

21. A multiphase regulator including at least one modulation system connected to a plurality of phases, each of the phases including a pair of switches driven by a corresponding driving circuit so as to supply a suitable output voltage value to an output terminal of the multiphase regulator, the multiphase regulator comprising:

a PWM signal generator connected to a modulator of the modulation system for supplying modulation signals to the phases;

a current sharing control circuit receiving the currents of the phases; and

an error comparator having a first input terminal receiving a reference voltage value, and a second input terminal connected, through a first impedance, to the output terminal and, through a second impedance, to an output terminal of the error comparator,

wherein the modulation system comprises;

a multiphase regulator of the interleaving type having a plurality of phases;

a PWM signal comparator block for the phases; and

a modulator supplying a plurality of ramp signals to the PWM signal comparator block, the modulator comprising control logic for determining a reset sequence of the ramp signals.

22. The multiphase regulator according to claim 21, wherein the current sharing control circuit supplies a plurality of balance voltages that are added by a plurality of adder nodes to a signal supplied on the output terminal of the error comparator.

23. The multiphase regulator according to claim 21, wherein the current sharing control circuit supplies a plurality of minimum voltage references connected to a plurality of supply terminals of the modulator, and the output terminal of the error comparator is connected to a control terminal of the PWM signal generator.