Semiconductor Device

• US 20110133828A1
• Filed: 12/09/2010
• Published: 06/09/2011
• Est. Priority Date: 06/06/2003
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kimura, Hajime
• Granted Patent: US 8,284,128 B2
• Time in Patent Office: Days
• US Class Current: 327/566
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 3/3241 the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
• CPC Class Codes: G09G 3/325 the data current flowing through the driving transistor during a setting phase, e.g. by using a switch for connecting the driving transistor to the data driver
• CPC Class Codes: G09G 3/3283 in which the data driver supplies a variable data current for setting the current through, or the voltage across, the light-emitting elements

Abstract

A semiconductor device is provided in which a transistor which supplies a current to a load (an EL pixel and a signal line) can supply an accurate current without being affected by a variation. A voltage of each terminal of a transistor is controlled by using a feedback circuit using an amplifier circuit. A current Idata is inputted from a current source circuit to a transistor and a gate-source voltage (a source potential) required for the transistor to flow the current Idata is set by using the feedback circuit. The feedback circuit is controlled to operate so that a drain potential of the transistor becomes a predetermined potential. Then, a gate voltage required to flow the current Idata is set. By using the set transistor, an accurate current can be supplied to the load (an EL element and a signal line). As a drain potential can be controlled, the kink effect can be reduced.

Claims

1. A semiconductor device comprising:

a first transistor having a first terminal and a second terminal;

a second transistor having a first terminal and a second terminal;

a third transistor having a gate, a first terminal and a second terminal;

an amplifier circuit having a first input terminal, a second input terminal and an output terminal; and

a current source circuit,

wherein the first terminal of the first transistor is electrically connected to the first input terminal of the amplifier circuit and the current source circuit,

wherein the second terminal of the first transistor is electrically connected to the first terminal of the third transistor,

wherein the first terminal of the second transistor is electrically connected to the output terminal of the amplifier circuit, and

wherein the second terminal of the second transistor is electrically connected to the gate of the third transistor.

2. The semiconductor device according to claim 1, wherein the second input terminal of the amplifier circuit is connected to a wiring.

3. The semiconductor device according to claim 1, wherein the second terminal of the third transistor is connected to a wiring.

4. The semiconductor device according to claim 1,

wherein the semiconductor device further comprises a capacitor having a first terminal and a second terminal,

wherein the first terminal of the capacitor is electrically connected to the second terminal of the second transistor and the gate of the third transistor, and

wherein the second terminal of the capacitor is connected to a wiring.

5. A semiconductor device comprising:

a first transistor having a first terminal and a second terminal;

a second transistor having a first terminal and a second terminal;

a third transistor having a gate, a first terminal and a second terminal;

a fourth transistor having a first terminal and a second terminal;

an amplifier circuit having a first input terminal, a second input terminal and an output terminal; and

a current source circuit,

wherein the first terminal of the first transistor is electrically connected to the first input terminal of the amplifier circuit and the current source circuit,

wherein the second terminal of the first transistor is electrically connected to the first terminal of the third transistor and a first terminal of the fourth transistor,

wherein the first terminal of the second transistor is electrically connected to the output terminal of the amplifier circuit, and

wherein the second terminal of the second transistor is electrically connected to the gate of the third transistor.

6. The semiconductor device according to claim 5, wherein the second input terminal of the amplifier circuit is connected to a wiring.

7. The semiconductor device according to claim 5, wherein the second terminal of the third transistor is connected to a wiring.

8. The semiconductor device according to claim 5,

wherein the semiconductor device further comprises a capacitor having a first terminal and a second terminal,

wherein the first terminal of the capacitor is electrically connected to the second terminal of the second transistor and the gate of the third transistor, and

wherein the second terminal of the capacitor is connected to a wiring.

9. The semiconductor device according to claim 5, wherein the second terminal of the fourth transistor is electrically connected to a load.

10. The semiconductor device according to claim 9, wherein the load is one of a resistor, a transistor, an EL element, a current source circuit configured with a transistor, a capacitor, or a switch, a wiring connected to a circuit, a signal line, and a signal line and a pixel connected to the signal line.