RESISTIVE MEMORY DEVICES HAVING A NOT-AND (NAND) STRUCTURE

• US 20110134676A1
• Filed: 12/04/2009
• Published: 06/09/2011
• Est. Priority Date: 12/04/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Lastras-Montano, Luis A., Franceschini, Michele M., Rajendran, Bipin, Breitwisch, Matthew J., Ditlow, Gary S., Montoye, Robert K.
• Granted Patent: US 8,107,276 B2
• Time in Patent Office: Days
• US Class Current: 365/49.1
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 15/046 using non-volatile storage elements
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 2013/0088 Write with the simultaneous writing of a plurality of cells
• CPC Class Codes: G11C 2013/0092 Write characterized by the shape, e.g. form, length, amplitude of the write pulse
• CPC Class Codes: G11C 2213/75 Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor

Abstract

Resistive memories having a not-and (NAND) structure including a resistive memory cell. The resistive memory cell includes a resistive memory element for storing a resistance value and a memory element access device for controlling access to the resistive memory element. The memory element access device is connected in parallel to the resistive memory element.

Claims

1. A memory comprising:

a first resistive memory cell comprising;

a resistive memory element for storing a resistance value; and

a memory element access device for controlling access to the resistive memory element, the memory element access device connected in parallel to the resistive memory element.

2. The memory of claim 1, wherein the resistive memory element is a phase change memory (PCM) element.

3. The memory of claim 1, further comprising a second resistive memory cell connected in series to the first resistive memory cell.

4. The memory cell of claim 3, further comprising a memory cell access device for controlling access to the first resistive memory cell and the second resistive memory cell, the memory cell access device connected in series with the first resistive memory cell and the second resistive memory cell.

5. The memory of claim 3, wherein the second resistive memory cell comprises a second resistive memory element for storing a resistance value and a second memory element access device connected in parallel to the second resistive memory element, the second memory element access device for controlling access to the second resistive memory element.

6. The memory of claim 1, wherein the memory element access device is a field effect transistor (FET) including two diffusions, the resistive memory element is a PCM element including a first side connected to one of the FET diffusions and a second side connected to the other FET diffusion.

7. A memory comprising:

a group of resistive memory cells comprising;

a plurality of resistive memory cells connected to each other in a series having two extremes, each resistive memory cell in the group comprising;

a resistive memory element for storing a resistance value; and

a memory element access device for controlling access to the resistive memory element, the memory element access device connected in parallel to the resistive memory element; and

a group access device for controlling access to the resistive memory cells, the group access device connected to one of the extremes.

8. The memory of claim 7, wherein the resistive memory elements are phase change memory (PCM) elements.

9. The memory of claim 7, further comprising a second group access device for controlling access to the resistive memory cells, the second group access device connected to a different extreme than the group access device.

10. The memory of claim 7, further comprising a second group of resistive memory cells connected in parallel to the group of resistive memory cells.

11. The memory of claim 7, further comprising an additional resistive memory cell connected to the group of resistive memory cells, the additional resistive memory cell comprising:

a resistive memory element for storing a resistance value; and

a memory element access device for controlling access to the resistive memory element, the memory element access device connected in a series having two extremes to the resistive memory element, each extreme connected to one of a power supply, a ground, and circuitry for controlling a voltage of the extreme.

12. The memory of claim 7, wherein the memory element access devices are field effect transistors (FETs) including two diffusions, and the resistive memory elements are PCM elements each including a first side connected to one of the FET diffusions of a FET and a second side connected to the other FET diffusion of the FET.

13. The memory of claim 7, wherein the memory is operable as a content addressable memory (CAM) searching for a stored word, wherein for each bit in the stored word two corresponding resistive memory cells in the group are programmed.

14. The memory of claim 13, wherein the CAM is a ternary CAM.

15. A method for writing to memory, the method comprising:

raising a voltage level at a first extreme of a group of resistive memory cells that are connected to each other in a series having two extremes including the first extreme and a second extreme, each resistive memory cell in the group including a resistive memory element for storing a resistance value and a memory element access device for controlling access to the resistive memory element, the memory element access device connected in parallel to the resistive memory element, the group connected to a group access device at one of the extremes;

turning off the memory element access devices in the resistive memory cells;

programming the resistive memory cells in the group to a reset state, the programming including turning on the group access device for the group, turning on the memory element access devices in the resistive memory cells in the group, turning off the memory element access devices in the group, and turning off the group access device for the group;

programming selected resistive memory cells in the group to a set state, the programming including turning on the group access device for the group, turning on the memory element access devices in the resistive memory cells in the group, turning off the memory element access devices in the selected resistive memory cells in the group, and turning off the group access device for the group.

16. The method of claim 15, wherein the turning off the memory element access devices in the selected resistive memory cells in the group is performed in sequence.

17. The method of claim 15, wherein the turning off the memory element access devices in the group is performed in sequence.

18. The method of claim 15, wherein the reset state is a high resistance state and the set state is a low resistance state.

19. The method of claim 15, wherein the resistive memory cells are phase change memory (PCM) cells.

20. The method of claim 15, wherein the selected resistive memory cells includes all of the resistive memory cells in the group.