PROCESSOR POWER MANAGEMENT

• US 20110138197A1
• Filed: 12/09/2010
• Published: 06/09/2011
• Est. Priority Date: 12/09/2009
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: LEE, Sejoong, LAKSHMANAN, Karthik Singaram
• Granted Patent: US 8,479,026 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method comprises operating a processor at a first power control strategy. Such a method further comprises determining whether a workload of a task running on a processor has fallen below a lower threshold, and changing to a second power control strategy to operate the processor based on determining that the workload of the task has fallen below the lower threshold.

Claims

1. A method, comprising:

operating a processor at a first power control strategy;

determining whether a workload of a task running on a processor has fallen below a lower threshold; and

changing to a second power control strategy to operate the processor based on determining that the workload of the task has fallen below the lower threshold.

2. The method of claim 1 wherein the first power control strategy includes a continuous clock frequency.

3. The method of claim 1 wherein the second power control strategy initially includes a lower frequency for operating the processor and then switches to a higher frequency based on the task not completing by a marker point in time.

4. The method of claim 3 wherein the second power control strategy includes the processor'"'"'s frequency remaining at the lower frequency based on the task completing by the marker point in time.

5. The method of claim 3 further comprising changing from the second power control strategy to the first power control strategy based on the task not completing by the marker point in time.

6. The method of claim 1 further comprising starting a marker timer upon starting the task, said marker timer expiring at a marker point in time, said marker point in time being a predetermined portion of a maximum time the task is allowed to complete.

7. The method of claim 6 further comprising determining whether the task has completed upon expiration of the marker timer and controlling a processor frequency based on whether or not the task has completed upon expiration of the marker timer.

8. The method of claim 1 further comprising running a plurality of tasks on the processor and wherein changing to the second power control strategy is based on determining that the workload of any of the tasks has fallen below the lower threshold.

9. The method of claim 1 further comprising:

determining whether the workload of the task exceeds an upper threshold; and

changing from the second power control strategy to the first power control strategy based on determining that the workload of the task has increased above the upper threshold.

10. The method of claim 9 wherein the lower threshold is 40% and the upper threshold is 75%.

11. The method of claim 9 further comprising providing a programming interface for a user to program the lower and upper thresholds.

12. A system, comprising:

a processor; and

a power and clock supply coupled to said processor;

wherein said processor asserts an operating point signal to said power and clock supply to cause the power and clock supply to implement an operating point for the processor; and

wherein the processor asserts said operating point signal to cause the power and clock supply to operate the processor in a first power controls strategy, determines whether a workload of a task running on the processor has fallen below a lower threshold and, based on the workload of the task being below the lower threshold, asserts said operating signal to cause the power and clock supply to operate the processor in a second power control strategy.

13. The system of claim 12 wherein the first power control strategy includes a continuous clock frequency.

14. The system of claim 12 wherein the second power control strategy initially includes a lower frequency for operating the processor and then switches to a higher frequency based on the task not completing by a marker point in time.

15. The system of claim 14 wherein the second power control strategy includes the processor'"'"'s frequency remaining at the lower frequency based on the task completing by the marker point in time.

16. The system of claim 14 wherein the processor asserts the signal to the power and clock supply to cause the power and clock supply to operate the processor in the first power control strategy based on determining that the task did not complete by the marker point in time

17. The system of claim 12 wherein the processor starts a marker timer upon starting the task, said marker timer expiring at a marker point in time, said marker point in time being a predetermined portion of a maximum time the task is allowed to complete.

18. The system of claim 17 wherein the processor determines whether the task has completed upon expiration of the marker timer and asserts the signal to the power and clock supply to control a frequency for the processor based on whether or not the task has completed upon expiration of the marker timer.

19. The system of claim 12 wherein a plurality of tasks run on the processor and wherein the change to the second power control strategy is based on determining that the workload of any of the tasks has fallen below the lower threshold.

20. A processor, comprising:

a processor core; and

a dynamic power control (DPC);

wherein said DPC asserts an operating point signal to a power and clock supply to cause the power and clock supply to implement an operating point for the processor; and

wherein the DPC asserts said operating point signal to request the power and clock supply to operate the processor in a first power controls strategy, determines whether a workload of a task running on the processor has fallen below a lower threshold and, based on the workload of the task being below the lower threshold, asserts said operating signal to request the power and clock supply to operate the processor in a second power control strategy.

21. The system of claim 20 wherein the first power control strategy includes a continuous clock frequency.

22. The system of claim 20 wherein the second power control strategy initially includes a lower frequency for operating the processor and then switches to a higher frequency based on the task not completing by a marker point in time.

23. The system of claim 22 wherein the second power control strategy includes the processor'"'"'s frequency remaining at the lower frequency based on the task completing by the marker point in time.

24. The system of claim 22 wherein the DPC asserts the signal to the power and clock supply to request the power and clock supply to operate the processor in the first power control strategy based on determining that the task did not complete by the marker point in time

25. The system of claim 20 wherein the DPC starts a marker timer upon starting the task, said marker timer expiring at a marker point in time, said marker point in time being a predetermined portion of a maximum time the task is allowed to complete.

26. The system of claim 25 wherein the DPC determines whether the task has completed upon expiration of the marker timer and asserts the signal to the power and clock supply to control a frequency for the processor based on whether or not the task has completed upon expiration of the marker timer.