TECHNIQUES TO PERFORM FORWARD ERROR CORRECTION FOR AN ELECTRICAL BACKPLANE

• US 20110138250A1
• Filed: 12/09/2010
• Published: 06/09/2011
• Est. Priority Date: 01/04/2006
• Status: Active Grant

• Current Assignee: Andrei Ovchinnikov, Andrey Belogolovy, Ilango S. Ganga, Luke Chang
• Original Assignee: Andrei Ovchinnikov, Andrey Belogolovy, Ilango S. Ganga, Luke Chang
• Inventors: Ovchinnikov, Andrei, Belogolovy, Andrey, Ganga, Ilango S., Chang, Luke
• Granted Patent: US 8,108,756 B2
• Time in Patent Office: Days
• US Class Current: 714/758
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: H03M 13/33 Synchronisation based on error coding or decoding
• CPC Class Codes: H03M 13/63 Joint error correction and other techniques H03M13/31 and H03M13/33 take precedence
• CPC Class Codes: H03M 13/6312 Error control coding in combination with data compression
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0042 Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape H04L1/0067 takes precedence
• CPC Class Codes: H04L 1/0043 Realisations of complexity reduction techniques, e.g. use of look-up tables
• CPC Class Codes: H04L 1/0047 Decoding adapted to other signal detection operation in conjunction with sequence estimation or equalization H04L25/03286
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0058 Block-coded modulation
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 1/0072 Error control for data other than payload data, e.g. control data
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/041 using special codes as synchronising signal
• CPC Class Codes: Y02D 30/00 Reducing energy consumption in communication networks

Abstract

Techniques to perform forward error correction for an electrical backplane are described. An apparatus may comprise a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header. Other embodiments are described and claimed

Claims

1. An apparatus, comprising:

a physical layer logic to perform forward error correction (FEC) using a transcode bit to represent a two bit synchronization header, and to encode a physical coding sublayer (PCS) block by compressing the two bit synchronization header into said transcode bit, and to use one bit of the two bit synchronization header in the PCS block to represent parity information, the parity information and transcode bit to be placed in an FEC block prior to transmission of the FEC block over a physical medium.

2. The apparatus of claim 1, further comprising a FEC sublayer logic to perform the FEC.

3. The apparatus of claim 2, wherein the FEC sublayer is implemented by code executable on a processor.

4. The apparatus of claim 2, wherein the physical layer logic and the FEC sublayer are implemented by a combination of hardware and software.

5. The apparatus of claim 2, wherein the FEC sublayer comprises a plurality of hardware components forming a part of a hardware physical layer unit.

6. The apparatus of claim 1, wherein the FEC block has 2112 bits including 32 parity bits and 32 65-bit blocks with each 65-bit block including one transcode bit.

7. The apparatus of claim 6, wherein the 32 parity bits are placed at the end of the FEC block.

8. The apparatus of claim 1, wherein the PCS block has 66 bits including the two bit synchronization header.

9. The apparatus of claim 1, wherein the value of the transcode bit corresponds to the value of a second bit in the two bit synchronization header.

10. The apparatus of claim 1, comprising a forward error correction decoder and block synchronizer to decode a physical coding sublayer block of information by reconstructing said two bit synchronization header using said single bit.

11. The apparatus of claim 1, wherein the FEC sublayer further comprising:

an FEC encoder to perform the encode of the PCS block.

12. The apparatus of claim 2, wherein the FEC sublayer further comprising:

a reverse gearbox;

a compressor to couple to said reverse gearbox;

a selector to couple to said compressor;

a parity generator to couple to said compressor;

a multiplexer to couple to said compressor, selector and said parity generator;

a scrambler to couple to said multiplexer; and

a pseudo-noise generator to couple to said scrambler.

13. The apparatus of claim 2, comprising a forward error correction decoder and block synchronizer to comprise:

a descrambler;

a pseudo-noise generator to couple to said descrambler;

a synchronizer to couple to said descrambler;

a decoder to couple to said synchronizer;

an error monitor to couple to said decoder; and

a reconstructor to couple to said decoder.

14. A method comprising:

performing forward error correction (FEC) using a transcode bit to represent a two bit synchronization header, said performing comprising;

encoding a physical coding sublayer (PCS) block of information by compressing said two bit synchronization header into said transcode bit;

using one bit of the two bit synchronization header in the PCS block to represent parity information; and

placing said transcode bit and said parity information in an FEC block prior to transmission of the FEC block over a physical medium.

15. The method of claim 14, wherein the PCS block has 66 bits including the two bit synchronization header.

16. The method of claim 14, wherein the value of the transcode bit corresponds to the value of a second bit in the two bit synchronization header.

17. The method of claim 14, comprising:

receiving PCS blocks of information;

compressing two synchronization bits from each PCS block to a transcode bit; and

generating the forward error correction block using said PCS blocks and said parity information.

18. The method of claim 17, wherein the FEC block has 2112 bits including 32 parity bits and 32 65-bit blocks with each 65-bit block including one transcode bit.

19. The method of claim 18, wherein the 32 parity bits are placed at the end of the FEC block.

20. The method of claim 14, comprising:

decoding a physical medium attachment (PMA) sublayer block of information by reconstructing said two bit synchronization header using said transcode bit.