THIN FILM TRANSISTOR AND METHOD OF FABRICATING THE SAME

• US 20110140097A1
• Filed: 09/21/2010
• Published: 06/16/2011
• Est. Priority Date: 12/11/2009
• Status: Active Grant

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Bak, Jun Yong, CHEONG, Woo Seok, Chung, Sung Mook
• Granted Patent: US 8,563,356 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Provided are a thin film transistor in which an oxide semiconductor combined with a nitride containing boron or aluminum is applied to a channel layer and a method of fabricating the same. The thin film transistor in which an oxide semiconductor combined with a nitride containing boron or aluminum is applied to a channel layer exhibits significantly improved mobility and increased stability at a high temperature.

Claims

1. A thin film transistor comprising:

source and drain electrodes, a channel layer, a gate insulating layer and a gate electrode disposed on a substrate,

wherein the channel layer includes an oxide semiconductor combined with a nitride containing boron or aluminum.

2. The thin film transistor of claim 1, further comprising a channel protection layer formed of at least one insulating material selected from the group consisting of AlOx, SiNx and SiOx on the channel layer.

3. The thin film transistor of claim 1, wherein the thin film transistor has a top gate coplanar structure in which source and drain electrodes, a channel layer, a gate insulating layer and a gate electrode are sequentially stacked on a substrate, a top gate staggered structure in which a channel layer, source and drain electrodes, a gate insulating layer and a gate electrode are sequentially stacked on a substrate, a bottom gate coplanar structure in which a gate electrode, a gate insulating layer, source and drain electrodes and a channel layer are sequentially stacked on a substrate or a bottom gate staggered structure in which a gate electrode, a gate insulating layer, a channel layer and source and drain electrodes are sequentially stacked on a substrate.

4. The thin film transistor of claim 1, wherein the oxide semiconductor is formed of at least one selected from the group consisting of ZnO, In—

Zn—

O, Zn—

Sn—

O, In—

Ga—

ZnO, Zn—

In—

Sn—

O, In—

Ga—

O and SnO₂.

5. The thin film transistor of claim 1, wherein the nitride containing boron or aluminum is included such that the boron or aluminum exists within a range of 0.01 to 50 at % on the basis of the total atomic weight of metal atoms of an oxide semiconductor constituting the semiconductor thin film.

6. The thin film transistor of claim 1, wherein the nitride containing boron or aluminum includes BN or AlN

7. The thin film transistor of claim 1, wherein the gate insulating layer is formed of at least one insulating material selected from the group consisting of AlOx, SiNx and SiOx.

8. The thin film transistor of claim 2, wherein the thin film transistor has a top gate coplanar structure in which source and drain electrodes, a channel layer, a gate insulating layer and a gate electrode are sequentially stacked on a substrate, a top gate staggered structure in which a channel layer, source and drain electrodes, a gate insulating layer and a gate electrode are sequentially stacked on a substrate, a bottom gate coplanar structure in which a gate electrode, a gate insulating layer, source and drain electrodes and a channel layer are sequentially stacked on a substrate or a bottom gate staggered structure in which a gate electrode, a gate insulating layer, a channel layer and source and drain electrodes are sequentially stacked on a substrate.

9. The thin film transistor of claim 2, wherein the oxide semiconductor is formed of at least one selected from the group consisting of ZnO, In—

Zn—

O, Zn—

Sn—

O, In—

Ga—

ZnO, Zn—

In—

Sn—

O, In—

Ga—

O and SnO₂.

10. The thin film transistor of claim 2, wherein the nitride containing boron or aluminum is included such that the boron or aluminum exists within a range of 0.01 to 50 at % on the basis of the total atomic weight of metal atoms of an oxide semiconductor constituting the semiconductor thin film.

11. The thin film transistor of claim 2, wherein the nitride containing boron or aluminum includes BN or AlN

12. The thin film transistor of claim 2, wherein the gate insulating layer is formed of at least one insulating material selected from the group consisting of AlOx, SiNx and SiOx.

14. The method of claim 8, further comprising forming a channel protection layer on the channel layer using an insulating material, wherein the channel protection layer is patterned together with the channel layer.

15. The method of claim 8, wherein when the channel layer is formed, the oxide semiconductor is formed of at least one material selected from the group consisting of ZnO, In—

Zn—

O, Zn—

Sn—

O, In—

Ga—

ZnO, Zn—

In—

Sn—

O, In—

Ga—

O and SnO₂, and the nitride containing boron or aluminum is included such that the boron or aluminum exists within a range of 0.01 to 50 at % on the basis of the total atomic weight of metal atoms of an oxide semiconductor constituting the semiconductor thin film.

16. The method of claim 8, wherein the channel layer is formed by depositing the oxide semiconductor combined with the nitride containing boron or aluminum to a thickness of 5 to 100 nm by sputtering, pulsed laser deposition (PLD) or ion-beam deposition at room temperature to 300°

C., and by performing post-annealing at a temperature below 600°

C.

17. The method of claim 9, wherein the channel protection layer is formed to a thickness of 1 nm to 20 nm using at least one insulating material selected from the group consisting of AlOx, SiNx and SiOx by chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering.

18. The method of claim 8, wherein when the channel layer is patterned, the patterning is performed using photoresist, and etching is performed by dry or wet etching or ion milling.

19. The method of claim 9, wherein when the channel protection layer is patterned, the patterning is performed using photoresist, and etching is performed by dry or wet etching or ion milling.

13. A method of fabricating a thin film transistor, comprising:

forming source and drain electrodes, a channel layer, a gate insulating layer and a gate electrode on a substrate, wherein the channel layer is formed of a semiconductor thin film formed of an oxide semiconductor combined with a nitride containing boron or aluminum; and

patterning the channel layer.