REVERSE SIDE ENGINEERED III-NITRIDE DEVICES

• US 20110140172A1
• Filed: 12/10/2009
• Published: 06/16/2011
• Est. Priority Date: 12/10/2009
• Status: Active Grant

• Current Assignee: Transphorm Technology, Inc. (Kohlberg Kravis Roberts & Company LP)
• Original Assignee: Transphorm, Inc (Kohlberg Kravis Roberts & Company LP)
• Inventors: Lal, Rakesh K., Mishra, Umesh, Chu, Rongming
• Granted Patent: US 8,389,977 B2
• Time in Patent Office: Days
• US Class Current: 257/194
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/03002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/03464 Electroless plating
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/06183 On contiguous sides of the body
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/291 Oxides or nitrides or carbides, e.g. ceramics, glass
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/6609 Diodes
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/1032 : III-V
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13064 : High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]

Abstract

Group III-nitride devices are described that include a stack of III-nitride layers, passivation layers, and conductive contacts. The stack includes a channel layer with a 2DEG channel, a barrier layer and a spacer layer. One passivation layer directly contacts a surface of the spacer layer on a side opposite to the channel layer and is an electrical insulator. The stack of III-nitride layers and the first passivation layer form a structure with a reverse side proximate to the first passivation layer and an obverse side proximate to the barrier layer. Another passivation layer is on the obverse side of the structure. Defected nucleation and stress management layers that form a buffer layer during the formation process can be partially or entirely removed.

Claims

1. A group III-nitride device, comprising:

a stack of III-nitride layers, wherein the stack includes a channel layer, a barrier layer directly adjacent to the channel layer and a spacer layer directly adjacent to a side of the channel layer opposite to the barrier layer, wherein the channel layer includes a 2DEG channel in the channel layer adjacent to the barrier layer;

a first passivation layer directly contacting a surface of the spacer layer on a side opposite to the channel layer, wherein the first passivation layer is an electrical insulator and the stack of III-nitride layers and the first passivation layer form a structure with a reverse side proximate to the first passivation layer and an obverse side proximate to the barrier layer;

a second passivation layer on the obverse side of the structure; and

one or more conductive contacts electrically connected to the 2DEG channel.

2. The device of claim 1, wherein the first passivation layer and the second passivation layer each have a sufficiently large bandgap, sufficiently low bulk defect density and sufficiently low interface density so that breakdown of the device is improved in comparison with a device having the stack of III-nitride layers and lacking the first passivation layer and the second passivation layer.

3. The device of claim 1, wherein the first passivation layer has an active interface state density of less than 1012/cm2 and an active bulk trap density less than 1 020/cm3.

4. The device of claim 1, wherein the first passivation layer or the second passivation layer is formed of an inorganic dielectric material.

5. The device of claim 4, wherein the first passivation layer or the second passivation layer includes silicon nitride, silicon dioxide, silicon oxynitride, alumina or aluminum nitride.

6. The device of claim 1, wherein the first passivation layer or the second passivation layer is an organic dielectric material.

7. The device of claim 6, wherein the first passivation layer or the second passivation layer includes an organic resin.

8. The device of claim 7, wherein the organic resin includes one of polyimide, benzocyclobutene (BCB) or SU8.

9. The device of claim 1, wherein the passivation layer includes a stack of at least one organic dielectric material and at least one inorganic dielectric material.

10. The device of claim 1, wherein the conductive contact is electrically connected to the reverse side of the structure.

11. The device of claim 1, wherein the stack of III-nitride layers is between 0.5 and 30 microns thick.

12. The device of claim 1, further comprising a gate contact and a gate dielectric, wherein the gate dielectric is between the stack of III-nitride layers and the second passivation layer.

13. The device of claim 1, wherein:

one of the one or more conductive contacts is a gate contact on the obverse side of the structure;

one of the conductive contacts is a source contact on the obverse side of the structure;

one of the conductive contacts is a drain contact on the reverse side of the structure; and

the second passivation layer covers an entirety of the obverse side of the structure including a space between the gate contact and the source contact.

14. The device of claim 1, further comprising:

a nucleation and stress management layer contacting the spacer layer; and

a mother substrate that includes silicon, wherein the nucleation and stress management layer is between the stack of III-nitride layers and the mother substrate;

wherein the device has a first portion including the stack of III-nitride layers and a second portion including the stack of III-nitride layers, the nucleation and stress management layer, and the mother substrate, the second portion forming an exoskeleton and the first portion being free of the mother substrate and the nucleation and stress management layer.

15. The device of claim 14, further comprising a dielectric layer on a side of the mother substrate that is opposite to the stack of III-nitride layers.

16. The device of claim 15, further comprising a conductive layer, wherein the dielectric layer is between a metallization layer and the mother substrate.

17. The device of claim 16, wherein the exoskeleton has a thin portion and a thick portion, wherein the mother substrate in the thin portion is thinner than the mother substrate in the thick portion and the conductive layer does not extend into the thick portion of the exoskeleton.

18. The device of claim 17, wherein the mother substrate in the thin portion is between about 10 and 50 microns.

19. The device of claim 14, further comprising a conductive layer on the obverse side that is connected to a conductive pad in the second portion.

20. The device of claim 14, wherein the exoskeleton maintains sufficient strain in the stack of III-nitride layers to create a 2DEG in the channel layer.

21. The device of claim 14, wherein the second passivation layer is confined to the first portion.

22. The device of claim 14, further comprising at least one of a control, protection, synchronization or drive circuit on the exoskeleton in either the silicon or III-nitride active region.

23. A method of forming a device, comprising:

forming a nucleation layer on a mother substrate, wherein the nucleation layer includes AlN;

forming a stress management layer on the nucleation layer that is on the mother substrate, wherein the stress management layer includes a III-nitride material;

forming a stack of III-nitride layers on the stress management layer, wherein forming the stack includes forming a channel layer with a 2DEG channel therein, the stacking having an obverse face opposite to the stress management layer;

attaching the obverse face of the stack to a carrier wafer;

removing an entirety of the mother substrate, the nucleation layer and the stress management layer, wherein the removing step exposes a reverse surface of the stack; and

passivating the reverse surface with a dielectric layer.

24. The method of claim 23, further comprising forming conductive contacts that are electrically connected to the 2DEG channel.

25. The method of claim 23, wherein:

the stack of III-nitride layers includes a barrier layer on a first side of the channel layer and a spacer layer on a second side of the channel layer;

the spacer layer includes an etch stop layer; and

the removing step etches to the etch stop layer.

26. The method of claim 23, further comprising forming an external contact to the 2DEG channel, wherein the external contacts extends through the dielectric layer.

27. The method of claim 23, further comprising fabricating one of a diode or a transistor in the stack of III-nitride layers.

28. A method of forming a device, comprising:

forming a nucleation layer on a mother substrate, wherein the nucleation layer includes AlN;

forming a stress management layer on the nucleation layer that is on the mother substrate, wherein the stress management layer includes a III-nitride material;

forming a stack of III-nitride layers on the stress management layer, wherein forming the stack includes forming a channel layer with a 2DEG channel therein; and

removing at least a portion of the mother substrate, a portion of the nucleation layer and a portion of the stress management layer, wherein the removing step only removes a portion of the mother substrate and forms a thin exoskeleton portion and a thick exoskeleton portion, wherein the mother substrate is thinner in the thin exoskeleton portion than in the thick exoskeleton portion.

29. The method of claim 28, wherein:

the stack of III-nitride layers includes a barrier layer on a first side of the channel layer and a spacer layer on a second side of the channel layer;

the spacer layer includes an etch stop layer; and

the removing step etches to the etch stop layer.