SURROUND GATE ACCESS TRANSISTORS WITH GROWN ULTRA-THIN BODIES

• US 20110140184A1
• Filed: 02/14/2011
• Published: 06/16/2011
• Est. Priority Date: 07/06/2005
• Status: Active Grant

• Current Assignee: Leonard Forbes
• Original Assignee: Leonard Forbes
• Inventors: Forbes, Leonard
• Granted Patent: US 8,115,243 B2
• Time in Patent Office: Days
• US Class Current: 257/296
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383

Abstract

A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid phase epitaxial growth process to avoid difficulties with forming sub-lithographic structures via etching processes. The body has ultra-thin dimensions and provides controlled short channel effects with reduced need for high doping levels. Buried data/bit lines are formed in an upper surface of a substrate from which the transistors extend. The transistor can be formed asymmetrically or offset with respect to the data/bit lines. The offset provides laterally asymmetric source regions of the transistors. Continuous conductive paths are provided in the data/bit lines which extend adjacent the source regions to provide better conductive characteristics of the data/bit lines, particularly for aggressively scaled processes.

Claims

1. An access array for memory cells comprising:

a semiconductive substrate;

a plurality of first conductors formed in a first direction along a surface of the substrate;

a plurality of transistors formed on the surface of the substrate so as to be offset from associated first conductors and at least partially connected to the associated first conductors; and

a plurality of second conductors formed in a second direction and electrically connected with associated transistors such that the transistors can be turned on and off by application of appropriate potentials to the second conductors.

2. The access array of claim 1, further comprising a plurality of charge storage devices connected with corresponding transistors such that each charge storage device and the corresponding transistor together define a memory cell of a memory array.

3. The access array of claim 2, wherein a predetermined charge can be provided to or removed from the charge storage devices via the corresponding transistors and associated first and second conductors to effect write operations to the memory cells.

4. The access array of claim 2, wherein the charge storage devices are stacked on top of the corresponding transistors.

5. The access array of claim 1, wherein the transistors comprise a transistor body and source regions are formed adjacent lower regions of the transistor bodies which overlie the associated first conductors and wherein continuous conductive paths are defined extending along the first conductors and adjacent the source regions.

6. The access array of claim 5, wherein drain regions are formed at upper regions of the transistor and wherein the source regions are laterally asymmetric with respect to the transistor bodies due to the offset of the transistors with respect to the associated first conductors such that conduction channels formed by appropriate potentials applied to the first and second conductors are formed laterally asymmetrically in the transistors.

7. The access array of claim 1, wherein each transistor comprises a single crystalline body region, a multiple grain region formed at an upper end of the single crystalline region, a drain region formed in the multiple grain region, and a source region formed at a lower end of the single crystalline region overlapping the corresponding first conductor.

8. A method of forming transistor structures comprising:

forming a pillar vertically extending from a surface of a substrate;

growing a single crystalline semiconductive transistor body to extend vertically around the pillar;

forming a surround gate structure around the transistor body;

forming a source region adjacent lower portions of the transistor body; and

forming a drain region adjacent an upper portion of the transistor body.

9. The method of claim 8, wherein forming the transistor body further comprises forming a multiple grain region adjacent the upper portion of the single crystalline body so as to extend across a top of the pillar and wherein the drain region is formed to at least partially occupy the multiple grain region.

10. The method of claim 8, wherein growing the single crystalline transistor body comprises performing a solid phase epitaxial growth process.

11. The method of claim 8, further comprising forming a first conductor in the surface of the substrate and wherein the pillar and body are formed offset from the first conductor so as partially overlie the first conductor with a remainder extending beyond the first conductor.

12. The method of claim 11, wherein the source region is formed as a c-shaped region defined generally by the overlap of the body over the first conductor and wherein a continuous conductive path is defined in the first conductor extending adjacent the source region.