SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
First Claim
1. A semiconductor device includinga semiconductor substrate,a MISFET formed within a MISFET forming region of the semiconductor substrate,a first insulating film formed in the semiconductor substrate so as to surround the MISFET forming region,a well region a first conductivity type formed in the semiconductor substrate and arranged below the first insulating film so as to surround the MISFET forming region,the MISFET comprising:
- a semiconductor layer of a second conductivity type opposed to the first conductivity type formed in the semiconductor substrate, which serves as a drain region;
a base region of the first conductivity type formed in the semiconductor substrate such that the base region is formed over the semiconductor layer, in which a channel is to be formed;
a source region of the second conductivity type formed in the semiconductor substrate such that the source region is formed over the base region, which a side surface and an upper surface;
a trench formed in the semiconductor substrate, which has contacts with the semiconductor layer, the base region and the source region;
a gate insulating film formed inside the trench;
a gate electrode formed over the gate insulating film and inside the trench;
a second insulating film formed over the gate electrode and the upper surface of the source region;
a contact hole formed in the second insulating film and the semiconductor substrate, whose bottom is located lower than the upper surface of the source region, the contact hole having contacts with the source region and the base region; and
a source wiring formed in the contact hole electrically connected with the source region and the base region.
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Accused Products
Abstract
Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.
30 Citations
13 Claims
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1. A semiconductor device including
a semiconductor substrate, a MISFET formed within a MISFET forming region of the semiconductor substrate, a first insulating film formed in the semiconductor substrate so as to surround the MISFET forming region, a well region a first conductivity type formed in the semiconductor substrate and arranged below the first insulating film so as to surround the MISFET forming region, the MISFET comprising: -
a semiconductor layer of a second conductivity type opposed to the first conductivity type formed in the semiconductor substrate, which serves as a drain region; a base region of the first conductivity type formed in the semiconductor substrate such that the base region is formed over the semiconductor layer, in which a channel is to be formed; a source region of the second conductivity type formed in the semiconductor substrate such that the source region is formed over the base region, which a side surface and an upper surface; a trench formed in the semiconductor substrate, which has contacts with the semiconductor layer, the base region and the source region; a gate insulating film formed inside the trench; a gate electrode formed over the gate insulating film and inside the trench; a second insulating film formed over the gate electrode and the upper surface of the source region; a contact hole formed in the second insulating film and the semiconductor substrate, whose bottom is located lower than the upper surface of the source region, the contact hole having contacts with the source region and the base region; and a source wiring formed in the contact hole electrically connected with the source region and the base region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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Specification