Method of Filling Large Deep Trench with High Quality Oxide for Semiconductor Devices

• US 20110140228A1
• Filed: 12/15/2009
• Published: 06/16/2011
• Est. Priority Date: 12/15/2009
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Inc. (Alpha & Omega Semiconductor, Ltd.)
• Original Assignee: Alpha & Omega Semiconductor, Inc. (Alpha & Omega Semiconductor, Ltd.)
• Inventors: Wang, Xiaobin, Bhalla, Anup, Lee, Yeeheng
• Granted Patent: US 8,247,297 B2
• Time in Patent Office: Days
• US Class Current: 257/506
• CPC Class Codes: H01L 21/76202 using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO H01L21/76235 takes precedence; together with vertical isolation, e.g. LOCOS in a SOI substrate, H01L21/76264
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76227 the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method is disclosed for creating a semiconductor device structure with an oxide-filled large deep trench (OFLDT) portion having trench size TCS and trench depth TCD. A bulk semiconductor layer (BSL) is provided with a thickness BSLT>TCD. A large trench top area (LTTA) is mapped out atop BSL with its geometry equal to OFLDT. The LTTA is partitioned into interspersed, complementary interim areas ITA-A and ITA-B. Numerous interim vertical trenches of depth TCD are created into the top BSL surface by removing bulk semiconductor materials corresponding to ITA-B. The remaining bulk semiconductor materials corresponding to ITA-A are converted into oxide. If any residual space is still left between the so-converted ITA-A, the residual space is filled up with oxide deposition. Importantly, the geometry of all ITA-A and ITA-B should be configured simple and small enough to facilitate fast and efficient processes of oxide conversion and oxide filling.

Claims

1. A method of creating a semiconductor device structure with an oxide-filled large deep trench (OFLDT) portion having trench size TCS and trench depth TCD, the method comprises:

a) providing a bulk semiconductor layer (BSL), having a thickness BSLT>

TCD, and mapping out a large trench top area (LTTA) atop the BSL with its geometry equal to that of OFLDT;

b) partitioning the LTTA into interspersed, complementary interim areas ITA-A and ITA-B each of pre-determined geometry;

c) creating into the top BSL surface, a plurality of interim vertical trenches so as to remove bulk semiconductor materials corresponding to ITA-B till the depth TCD; and

d) converting;

the remaining bulk semiconductor materials corresponding to ITA-A into oxide and;

should there be any residual space left atop the LTTA, filling up the residual space with oxide.

2. The method of claim 1 wherein partitioning the LTTA further comprises insuring that the geometry of all ITA-A and all ITA-B are partitioned simple and small enough whereby facilitating:

d1) a fast, efficient conversion process of the remaining bulk semiconductor into high quality oxide; and

d2) a fast, efficient oxide filling process with high quality oxide.

3. The method of claim 1 wherein creating a plurality of interim vertical trenches further comprises:

simultaneously creating, into the top BSL surface, a plurality of deep active device trenches in an active device trench top area ADTTA mapped out atop the BSL and separate from the LTTA.

4. The method of claim 3 wherein simultaneously creating the deep active device trenches and the interim vertical trenches comprises:

c1) anisotropically etching out most volumetric portion of the deep active and interim vertical trenches; and

c2) isotropically etching out small remaining volumetric portion of the deep active and interim vertical trenches whereby causing them to have rounded corners to facilitate subsequent processing.

5. The method of claim 1 wherein converting the remaining bulk semiconductor materials is via thermal oxidation and filling up the residual space is via oxide deposition.

6. The method of claim 3 wherein converting the remaining bulk semiconductor materials corresponding to ITA-A into oxide further comprises simultaneously converting:

d1) a surface portion of the deep active device trench walls into oxide; and

d2) the remaining bulk semiconductor materials corresponding to ITA-A into oxide.

7. The method of claim 6 further comprising, after step d),

e) planarizing the top surface then selectively etching down the oxide in the ADTTA.

8. The method of claim 1 wherein the shape of each ITA-A is square, rectangle, circle, ellipse, hexagon or polygon.

9. The method of claim 1 wherein the size of each ITA-A is from about 0.5 micron to about 4 micron and the size of each ITA-B is from about 0.4 micron to about 3 micron.

10. The method of claim 1 wherein TCS is from about 10 micron to about 100 micron and TCD is from about 10 micron to about 50 micron.

11. The method of claim 3 wherein step d) further comprises:

d1) selectively forming an interim oxidation prevention layer upon the deep active device trenches; and

d2) selectively converting the remaining bulk semiconductor materials corresponding to ITA-A into oxide and, should there be any residual space left between the so-converted ITA-A, filling up the residual space with oxide.

12. The method of claim 11 further comprising:

e) removing the interim oxidation prevention layer and forming a liner oxide upon the deep active device trenches.

13. The method of claim 12 wherein selectively forming the interim oxidation prevention layer comprises forming a silicon nitride layer.

14. A method of forming a large deep oxide trench in a semiconductor substrate comprising:

a) forming, in the semiconductor substrate, a plurality of interim trenches separated by a corresponding number of remaining semiconductor mesas between the interim trenches; and

b) oxidizing the remaining semiconductor mesas until they are substantially converted to oxide.

15. The method of claim 14 further comprising:

c) filling up any remaining spaces of the interim trenches with insulating material.

16. The method of claim 15 wherein filling up any remaining spaces further comprises filling up any remaining spaces of the interim trenches with oxide.

17. The method of claim 14 wherein oxidizing the remaining semiconductor mesas is via thermal oxidation.

18. The method of claim 14 wherein oxidizing the remaining semiconductor mesas further comprises oxidizing the semiconductor mesas until all the semiconductor material in the mesas is converted to oxide.

19. A wide and deep oxide trench in a semiconductor substrate comprising vertical oxide ribs, being made of thermal oxide, interspersed throughout the wide and deep oxide trench.

20. The wide and deep oxide trench of claim 19 wherein any remaining spaces between the vertical oxide ribs are filled with an insulating material.

21. The wide and deep oxide trench of claim 19 wherein any remaining spaces between the vertical oxide ribs are filled with deposited oxide.

22. The wide and deep oxide trench of claim 19 wherein the vertical oxide ribs contain a small notch at their bottoms.