TECHNIQUES FOR FORMING SHALLOW TRENCH ISOLATION

• US 20110140229A1
• Filed: 12/16/2009
• Published: 06/16/2011
• Est. Priority Date: 12/16/2009
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jin, Been-Yih, Chau, Robert S., Pillarisetty, Ravi, Rachmady, Willy
• Application Number:
  US12/639,451
• Publication Number:
  US 20110140229A1
• Time in Patent Office: Days
• US Class Current: 257/506
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264

Abstract

Techniques are disclosed for shallow trench isolation (STI). The techniques can be used to form STI structures on any number of semiconductor materials, including germanium (Ge), silicon germanium (SiGe), and III-V material systems. In general, an interfacial passivation layer is used as a liner between the semiconductor surface (such as diffusion) and isolation materials within the STI. The interfacial layer provides a passivation layer on trench surfaces to restrict free bonding electrons of the substrate material. In addition, this passivation layer is oxidized, thereby effectively forming a bi-layer (passivation and oxidation sub-layers) to form an electrically defect free interface. The interfacial bi-layer structure can be implemented, for example, with materials that will covalently bond with free bonding electrons of the substrate materials, and that will oxidize to provide transition to oxide material.

Claims

1. A method for forming a shallow trench isolation structure, comprising:

etching to form a trench for shallow trench isolation on a semiconductor substrate, the trench having side and bottom surfaces; and

applying a passivation layer on the surfaces of the trench to restrict free bonding electrons at those trench surfaces.

2. The method of claim 1 further comprising:

partially oxidizing the passivation layer, thereby forming a bi-layer of passivation material and oxidized passivation material.

3. The method of claim 2 wherein the substrate includes germanium, the passivation material is silicon, and the oxidized passivation material is silicon dioxide.

4. The method of claim 1 further comprising at least one of:

prior to etching, patterning a hardmask for shallow trench isolation;

depositing dielectric oxide material into the trench, thereby providing an STI structure; and

planarizing the STI structure.

5. The method of claim 1 wherein the method is carried out on at least one of a blank substrate and a partially fabricated semiconductor growth structure.

6. The method of claim 1 wherein the passivation layer is epitaxially grown on the trench surfaces.

7. The method of claim 1 wherein the passivation layer covalently bonds to surface atoms on the trench surfaces.

8. The method of claim 8 wherein the passivation layer is thermally stable.

9. An integrated circuit device, comprising:

a semiconductor substrate having one or more trenches etched therein, each trench having side and bottom surfaces; and

a passivation layer on the surfaces of each trench to restrict free bonding electrons at those trench surfaces.

10. The device of claim 9 wherein the passivation layer is partially oxidized, thereby forming a bi-layer of passivation material and oxidized passivation material.

11. The device of claim 10 wherein the substrate includes germanium, the passivation material is silicon, and the oxidized passivation material is silicon dioxide.

12. The device of claim 9 further comprising:

a dielectric oxide material deposited into each trench, thereby providing one or more STI structures, wherein the one or more STI structures are planarized.

13. The device of claim 9 wherein the substrate is at least one of a blank substrate and a partially fabricated semiconductor growth structure.

14. The device of claim 9 wherein the passivation layer is epitaxially grown on the trench surfaces and covalently bonds to surface atoms on the trench surfaces.

15. The device of claim 9 wherein the device is integrated into a system including at least one of a processor, memory, and/or logic circuit.

16. A method for forming a shallow trench isolation structure, comprising:

etching to form one or more trenches for shallow trench isolation on a semiconductor substrate, each trench having side and bottom surfaces;

epitaxially growing a passivation layer on the surfaces of each trench to restrict free bonding electrons at those trench surfaces; and

partially oxidizing the passivation layer, thereby forming a bi-layer of passivation material and oxidized passivation material.

17. The method of claim 16 wherein the substrate includes germanium, the passivation material is silicon, and the oxidized passivation material is silicon dioxide.

18. The method of claim 16 further comprising:

depositing dielectric oxide material into the trench, thereby providing an STI structure; and

planarizing the STI structure.

19. The method of claim 16 wherein the method is carried out on at least one of a blank substrate and a partially fabricated semiconductor growth structure.

20. The method of claim 16 wherein the passivation layer covalently bonds to surface atoms on the trench surfaces, and is thermally stable.