HIGH-DENSITY INTER-PACKAGE CONNECTIONS FOR ULTRA-THIN PACKAGE-ON-PACKAGE STRUCTURES, AND PROCESSES OF FORMING SAME

• US 20110140268A1
• Filed: 09/24/2010
• Published: 06/16/2011
• Est. Priority Date: 12/16/2009
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Periaman, Shanggar, Ooi, Kooi Chi, Cheah, Bok Eng
• Granted Patent: US 8,987,896 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45 of an individual wire connector
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19106 : in a mirrored arrangement on two different side of a common die mounting substrate
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H05K 1/0298 : Multilayer circuits
• CPC Class Codes: H05K 1/111 : Pads for surface mounting, e.g. lay-out
• CPC Class Codes: H05K 1/183 : Components mounted in and supported by recessed areas of the printed circuit board
• CPC Class Codes: H05K 1/185 : Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 3/10 : in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
• CPC Class Codes: H05K 3/34 : by soldering
• CPC Class Codes: H05K 3/36 : Assembling printed circuits with other printed circuits H05K7/142 takes precedence
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

An apparatus includes a coreless mounting substrate and an interposer disposed on the coreless mounting substrate with a chip disposed in a recess in the interposer and upon the coreless substrate. The apparatus may include an inter-package solder bump in contact with an interconnect channel in the interposer, and a top chip package including a top package substrate and a top die disposed on the top package substrate. The top package substrate is in contact with the inter-package solder bump.

Claims

1. An apparatus, comprising:

a coreless mounting substrate

an interposer disposed on the coreless mounting substrate, wherein the interposer includes;

a die side and a land side that is parallel planar to the die side;

a chip recess that communicates to the die side and the land side, wherein the chip recess projects a footprint onto the coreless mounting substrate;

an interconnect channel that passes through the interposer, wherein the interconnect channel is electrically coupled to the coreless substrate by contact with a substrate bump; and

a trace in the coreless mounting substrate.

2. The apparatus of claim 1, further including a chip disposed on the coreless mounting substrate within the recess footprint and coupled to the trace.

3. The apparatus of claim 1, wherein the coreless mounting substrate exhibits a first stiffness and the interposer exhibits a second stiffness that is greater than the first stiffness.

4. The apparatus of claim 1, wherein the recess footprint is centered on a symmetry line that equally bisects the coreless substrate.

5. The apparatus of claim 1, wherein the recess footprint is asymmetrically located with respect to a symmetry line that equally bisects the coreless substrate.

6. The apparatus of claim 1, wherein the recess is a first recess, the apparatus further including a second recess spaced apart from the first recess, and wherein the second recess communicates to the die side and the land side.

7. The apparatus of claim 1, wherein the recess is a first recess, the apparatus further including:

a second recess spaced apart from the first recess, wherein the second recess communicates to the die side and the land side; and

a processor chip disposed on the coreless substrate in the first recess.

8. The apparatus of claim 1, wherein the recess is a first recess, the apparatus further including:

a second recess spaced apart from the first recess, wherein the second recess communicates to the die side and the land side; and

wherein the first recess footprint is asymmetrically located with respect to a symmetry line that equally bisects the coreless substrate.

9. The apparatus of claim 1, further including:

a first die disposed on the coreless substrate within the recess footprint; and

a subsequent die also disposed on the coreless substrate within the recess footprint.

10. The apparatus of claim 1, wherein interposer is a first interposer, and wherein the recess is a first recess, the apparatus further including:

a second recess spaced apart from the first recess, wherein the second recess communicates to the die side and the land side; and

a subsequent interposer disposed above the first interposer.

11. The apparatus of claim 1, wherein interposer is a first interposer, and wherein the recess is a first recess, the apparatus further including:

a second recess spaced apart from the first recess, wherein the second recess communicates to the die side and the land side;

a subsequent interposer disposed above the first interposer;

a first die disposed on the coreless substrate in the first recess; and

a second die disposed on the coreless substrate in the second recess, and where the first die and the second die are different respective sizes.

12. The apparatus of claim 1, wherein the recess is a first recess, the apparatus further including:

a second recess spaced apart from the first recess, wherein the second recess communicates to the die side and the land side;

a first chip disposed on the coreless substrate in the first recess; and

a second chip disposed on the coreless substrate in the second recess, wherein the second chip is wire-bonded to the coreless substrate.

13. The apparatus of claim 1, wherein the coreless substrate is a thin core substrate.

14. An apparatus, comprising:

a coreless mounting substrate;

an interposer disposed on the coreless mounting substrate, wherein the interposer includes;

a die side and a land side that is parallel planar to the die side;

a chip recess that communicates to the die side and the land side, wherein the chip recess projects a footprint onto the coreless mounting substrate;

an interconnect channel that passes through the interposer, wherein the interconnect channel is electrically coupled to the coreless substrate by contact with a substrate bump;

a chip disposed on the coreless substrate within the footprint;

an inter-package solder bump in contact with the interconnect channel; and

a top chip package including a top package substrate and a top die disposed on the top package substrate, wherein the top package substrate is in contact with the inter-package solder bump.

15. The apparatus of claim 14, wherein the recess footprint is asymmetrically located with respect to a symmetry line that equally bisects the coreless substrate.

16. The apparatus of claim 14, wherein the recess is a first recess, the apparatus further including a second recess spaced apart from the first recess, and wherein the second recess communicates to the die side and the land side.

17. The apparatus of claim 14, wherein the recess is a first recess, the apparatus further including:

a second recess spaced apart from the first recess, wherein the second recess communicates to the die side and the land side; and

wherein the chip is a processor chip disposed on the coreless substrate in the first recess.

18. The apparatus of claim 14, wherein the recess is a first recess, the apparatus further including:

a second recess spaced apart from the first recess, wherein the second recess communicates to the die side and the land side; and

wherein the first recess footprint is asymmetrically located with respect to a symmetry line that equally bisects the coreless substrate.

19. The apparatus of claim 14, further including:

wherein the chip is a first die disposed on the coreless substrate within the recess footprint; and

a subsequent die also disposed on the coreless substrate within the recess footprint.

20. The apparatus of claim 14, wherein interposer is a first interposer, and wherein the recess is a first recess, the apparatus further including:

a second recess spaced apart from the first recess, wherein the second recess communicates to the die side and the land side; and

a subsequent interposer disposed above the first interposer.

21. The apparatus of claim 14, wherein interposer is a first interposer, and wherein the recess is a first recess, the apparatus further including:

a second recess spaced apart from the first recess, wherein the second recess communicates to the die side and the land side;

a subsequent interposer disposed above the first interposer;

wherein the chip is a first die disposed on the coreless substrate in the first recess; and

a second die disposed on the coreless substrate in the second recess, and where the first die and the second die are different respective sizes.

22. The apparatus of claim 14, wherein the recess is a first recess, the apparatus further including:

a second recess spaced apart from the first recess, wherein the second recess communicates to the die side and the land side;

wherein the die is a first chip disposed on the coreless substrate in the first recess; and

a second chip disposed on the coreless substrate in the second recess, wherein the second chip is wire-bonded to the coreless substrate.

23. A computing system, comprising:

a coreless mounting substrate;

an interposer disposed on the coreless mounting substrate, wherein the interposer includes;

a die side and a land side that is parallel planar to the die side;

a chip recess that communicates to the die side and the land side, wherein the chip recess projects a footprint onto the coreless mounting substrate;

an interconnect channel that passes through the interposer, wherein the interconnect channel is electrically coupled to the coreless substrate by contact with a substrate bump;

a chip disposed on the coreless substrate within the footprint;

an inter-package solder bump in contact with the interconnect channel; and

a top chip package including a top package substrate and a top die disposed on the top package substrate, wherein the top package substrate is in contact with the inter-package solder bump; and

external memory coupled to the die.

24. The computing system of claim 23, wherein the computing system is part of one of a cellular telephone, a pager, a portable computer, a desktop computer, and a two-way radio.

25. A process comprising:

forming an interconnect channel in an interposer;

plating the interconnect channel with an electrical conductor;

removing metal spaced apart from the interconnect channel;

filling the interconnect channel with an electrical conductor;

forming a recess in the interposer to accommodate a microelectronic die;

mating the interposer to a coreless mounting substrate, wherein the recess projects a footprint onto the coreless substrate; and

attaching a microelectronic die to the coreless mounting substrate at the recess footprint.

26. The process of claim 25, further including forming an underfill between the microelectronic die and the coreless substrate.

27. The process of claim 25, wherein attaching the microelectronic die precedes mating the interposer to the coreless mounting substrate, and further including forming an underfill between the microelectronic die and the coreless substrate.

28. The process of claim 25, wherein the interposer is part of an unsingulated array of interposers, the method further including singulating the array of interposers after mating the interposer to the coreless mounting substrate.

29. The process of claim 25, wherein the interposer is part of an unsingulated array of interposers, the method further including singulating the array of interposers after attaching the microelectronic die to the coreless mounting substrate at the recess.

30. The process of claim 25, wherein the coreless mounting substrate, the die, and the interposer is a bottom package, the process further including:

forming an inter-package solder bump at the electrical conductor; and

assembling a top package to the bottom package by coupling the top package to the inter-package solder bump.

31. The process of claim 25, wherein the coreless mounting substrate, the die, and the interposer is a bottom package, the process further including:

forming an inter-package solder bump at the electrical conductor; and

assembling a top package to the bottom package by coupling the top package to the inter-package solder bump, wherein the top package includes a top mounting substrate and a wire-bonded die disposed on the top mounting substrate.

32. The process of claim 25, wherein the coreless mounting substrate, the die, and the interposer is a bottom package, the process further including:

forming an inter-package solder bump at the electrical conductor; and

assembling a top package to the bottom package by coupling the top package to the inter-package solder bump, wherein the top package includes a top mounting substrate and a flip-chip die disposed on the top mounting substrate.

33. The process of claim 25, wherein the coreless mounting substrate, the die, and the interposer is a bottom package, the process further including:

forming an inter-package solder bump at the electrical conductor; and

assembling a top package to the bottom package by coupling the top package to the inter-package solder bump, wherein the top package includes a top mounting substrate, a flip-chip die disposed above the top mounting substrate, and a wire-bonded die disposed above the top mounting substrate.