FUSE DRIVER CIRCUITS

• US 20110140713A1
• Filed: 12/10/2010
• Published: 06/16/2011
• Est. Priority Date: 12/11/2009
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Hall, James, Snowdon, Kenneth P., Newberry, William Robert, Yarborough, Roy
• Granted Patent: US 9,224,566 B2
• Time in Patent Office: Days
• US Class Current: 324/550
• CPC Class Codes: G01R 31/74 Testing of fuses
• CPC Class Codes: H01H 2085/466 with remote controlled forced fusing
• CPC Class Codes: H01H 85/46 Circuit arrangements not adapted to a particular application of the protective device

Abstract

Fuse driver circuits, fuse driver testing circuitry, and methods for testing the fuse driver circuits using the testing circuitry are described. In some embodiments, the fuse driver circuit can be made using a fuse, a NMOS transistor, and a PMOS transistor. The drain of the NMOS transistor can be connected to the negative end of the fuse. The source of the NMOS transistor can be connected to ground. The drain of the PMOS transistor can be connected to a positive end of the fuse. The NMOS and PMOS transistors provide enhanced robustness to the fuse driver circuit in both undervoltage and overvoltage conditions. Other embodiments are also described.

Claims

1. A fuse driver circuit, comprising:

a fuse;

a NMOS transistor having a drain of the NMOS transistor coupled to a negative end of the fuse and a source of the NMOS transistor coupled to ground; and

a PMOS transistor having a drain of the PMOS transistor coupled a positive end of the fuse.

2. The fuse driver circuit of claim 1, further comprising a first diode having the positive end of the diode coupled to a source of the PMOS transistor and the negative end of the diode coupled to a well of the PMOS transistor.

4. The fuse driver circuit of claim 1, further comprising a second diode having a positive end coupled to ground and a negative end coupled to a gate of the PMOS transistor.

5. The fuse driver circuit of claim 1, further comprising a third diode having a positive end coupled to ground and a negative end coupled to a gate of the NMOS transistor.

6. The fuse driver circuit of claim 1, wherein the NMOS transistor is a first NMOS transistor, and the fuse driver circuit further comprising a second NMOS transistor having the drain of the second NMOS transistor coupled to the positive end of the fuse, a source of the second NMOS transistor coupled to ground, the positive end of the fuse coupled to a first sense point, and the gate of the NMOS transistor coupled to a second sense point.

7. The fuse driver circuit of claim 1, wherein the PMOS transistor is a first PMOS transistor, and the fuse driver circuit further comprising a second PMOS transistor having a drain of the second PMOS transistor is coupled to the negative end of the fuse, a source of the second PMOS transistor coupled to a power supply (Vdd), the positive end of the fuse coupled to a first sense point, and a gate of the first NMOS transistor coupled to a third sense point.

8. The fuse driver circuit of claim 1, wherein the fuse is a polyfuse.

9. The fuse driver circuit of claim 1, further comprising a third NMOS transistor having the drain of the third NMOS transistor coupled to a positive end of the fuse and a source of the third NMOS transistor coupled to a negative end of the fuse.

10. The fuse driver circuit of claim 1, further comprising a fourth diode having a positive end of the fourth diode coupled to a negative end of the fuse and a negative end of the fourth diode coupled to a positive end of the fuse.

11. The fuse driver circuit of claim 10, wherein the fourth diode is a Schottky diode.

3. The fuse driver circuit of claim 3, wherein the first diode is selected from a group consisting of a Schottky diode, a P-N diode, a PNP-BJT, and a NMOS transistor.

12. A fuse driver circuit, comprising:

a fuse;

a first NMOS transistor having a drain of the first NMOS transistor coupled to a negative end of the fuse and a source of the first NMOS transistor coupled to ground; and

a second NMOS transistor having a drain of the second NMOS transistor coupled to a positive end of the fuse and a source of the second NMOS transistor coupled to a negative end of the fuse.

13. The fuse driver circuit of claim 12, wherein the fuse is a polyfuse.

14. A fuse driver circuit, comprising:

a fuse;

a NMOS transistor having a drain of the NMOS transistor coupled to a negative end of the fuse and a source of the NMOS transistor coupled to ground; and

a diode having a positive end of the diode coupled to a negative end of the fuse and a negative end of the diode coupled to a positive end of the fuse.

15. The fuse driver circuit of claim 14, wherein the diode is a Schottky diode.

16. The fuse driver circuit of claim 14, wherein the fuse is a polyfuse.

17. A method of testing a fuse driver circuit, comprising:

providing a circuit having a fuse, a first NMOS transistor having a drain of the first NMOS transistor coupled to a negative end of the fuse and a source of the first NMOS transistor coupled to ground, a first PMOS transistor having a drain of the first PMOS transistor coupled a positive end of the fuse;

providing a first sense point coupled to the positive end of the poly fuse;

providing a second NMOS transistor having a drain of the second NMOS transistor coupled to the positive end of the fuse, a source of the second NMOS transistor coupled to ground, and a gate of the second NMOS transistor coupled to a second sense point; and

turning on the first PMOS transistor and the second NMOS transistor, turning off the first NMOS transistor, and monitoring the current that passes through the first PMOS transistor using the first and second sense points.

18. The method of claim 17, further comprising

providing a second PMOS transistor having a drain of the second PMOS transistor coupled to the negative end of the fuse, a source of the second PMOS transistor coupled to a power supply (Vdd), and a gate of the second PMOS transistor coupled to a third sense point;

and

turning on the first NMOS transistor and the second PMOS transistor, turning off the first PMOS transistor, and monitoring the current that passes through the first NMOS transistor using the first and third sense points.